Editing Weak consistency

{{no footnotes|date=May 2017}}
The name '''weak consistency''' can be used in two senses. In the first sense, strict and more popular, '''weak consistency''' is one of the [[consistency model]]s used in the domain of [[concurrent programming]] (e.g. in [[distributed shared memory]], [[distributed transactions]] etc.). 

A protocol is said to support weak consistency if:
#All accesses to synchronization variables are seen by all processes (or nodes, processors) in the same order (sequentially) - these are synchronization operations. Accesses to critical sections are seen sequentially.
#All other accesses may be seen in different order on different processes (or nodes, processors).
#The set of both read and write operations in between different synchronization operations is the same in each process.

Therefore, there can be no access to a synchronization variable if there are pending write operations. And there can not be any new read/write operation started if the system is performing any synchronization operation.

In the second, more general, sense '''weak consistency''' may be applied to any consistency model weaker than [[sequential consistency]].

A stricter condition is [[strong consistency]], where parallel processes can observe only one consistent state.

==References==
<references />
* The original paper on weak ordering: M. Dubois, C. Scheurich and F. A. Briggs, ''Memory Access Buffering in Multiprocessors'', in Proceedings of 13th Annual [[International Symposium on Computer Architecture]] 14, 2 (June 1986), 434-442.
* [[Sarita Adve|Sarita V. Adve]], Mark D. Hill, ''[http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.42.5567 Weak ordering - a new definition]'', in Proceedings of the 17th Annual [[International Symposium on Computer Architecture]].

[[Category:Consistency models]]


{{compu-eng-stub}}