Editing Zero page

{{Short description|Memory page starting at address zero}}

{{use dmy dates|date=March 2020|cs1-dates=y}}
{{use list-defined references|date=December 2021}}
The '''zero page''' or '''base page''' is the block of memory at the very beginning of a [[computer]]'s [[address space]]; that is, the [[page (computer memory)|page]] whose starting address is zero. The size of a page depends on the context, and the significance of zero page memory versus higher addressed memory is highly dependent on machine architecture. For example, the [[Motorola 6800]] and [[MOS Technology 6502]] processor families treat the first 256 [[byte]]s of [[Computer memory|memory]] specially,<ref name="Student Papers in Computer Architecture"/> whereas many other processors do not.

Unlike more modern hardware, in the 1970s computer [[random-access memory|RAM]] speed was similar to that of  CPUs.{{fact|date=September 2022}} Thus it made sense to have few registers and use the main memory as an extended pool of extra registers. In machines with a relatively wide [[16-bit]] [[address bus]] and comparatively narrow [[8-bit]] [[bus (computing)|data bus]], calculating an address in memory could take several cycles. The zero page's one-byte address was smaller and therefore faster to read and calculate than other locations, making the zero page useful for high-performance code.

Zero page addressing now has mostly historical significance, since the developments in [[integrated circuit]] [[technology]] have made adding more registers to a CPU less expensive and CPU operations much faster than RAM accesses.

== Size ==
The actual size of the zero page in bytes is determined by the [[microprocessor]] design and in older designs, is often equal to the largest value that can be referenced by the processor's indexing registers. For example, the aforementioned 8-bit processors have 8-bit index registers and a page size of 256 bytes. Therefore, their zero page extends from address 0 to address 255.

== Computers with few CPU registers ==
In early computers, such as the [[PDP-8]], the zero page had a special fast [[addressing mode]], which facilitated its use for temporary [[computer storage|storage of data]] and compensated for the paucity of [[central processing unit|CPU]] [[processor register|register]]s.  The PDP-8 had only one register, so zero page addressing was essential.  In the original [[PDP-10#Registers|PDP-10]] KA-10 models, the available registers are simply the first 16 words, [[36-bit computing|36-bits]] long, of main memory.  Those locations can be accessed as both registers and memory locations.

Unlike more modern hardware, 1970s-era computer [[random-access memory|RAM]] was as fast as the CPU.  Thus, it made sense to have few registers and use the main memory as an extended pool of extra registers.  In machines with a [[16-bit]] [[address bus]] and [[8-bit]] [[bus (computing)|data bus]], accessing zero page locations could be faster than accessing other locations.  Since zero page locations could be addressed by a single [[byte]], the instructions accessing them could be shorter and hence faster-loading.

{{anchor|Direct addressing|Zero-page addressing}}For example, the [[MOS Technology 6502]] family has only one general purpose register: the accumulator.  To offset this limitation and gain a performance advantage, the 6502 is designed to make special use of the zero page, providing instructions whose [[operand]]s are eight bits, instead of 16, thus requiring fewer memory fetch cycles.  Many [[instruction set architecture|instructions]] are coded differently for zero page and non-zero page addresses; this is called ''zero-page addressing'' in 6502 terminology (it is called ''direct addressing'' in [[Motorola 6800]] terminology; the [[Western Design Center]] [[65C816]] also refers to zero page addressing as ''direct page addressing''):
<syntaxhighlight lang="nasm">
 LDA $12            ; zero page addressing
 LDA $0012          ; absolute addressing
</syntaxhighlight>

In 6502 assembly language, the above two instructions both accomplish the same thing: they load the value of memory location <code>$12</code> into the <code>.A</code> (accumulator) register (<code>$</code> is Motorola/MOS Technology assembly language notation for a hexadecimal number).  However, the first instruction is only two bytes long and requires three clock cycles to complete.  The second instruction is three bytes in length and requires four clock cycles to execute.  This difference in execution time could become significant in repetitive code.

{{anchor|Direct page|Direct page addressing}}Some processors, such as the [[Motorola 6809]] and the aforementioned WDC 65C816, implement a “direct page register” (<code>DP</code>) that tells the processor the starting address in [[RAM]] of what is considered to be zero page.  In this context, zero page addressing is notional; the actual access would not be to the physical zero page if <code>DP</code> is loaded with some address other than <code>$00</code> (or <code>$0000</code> in the case of the 65C816).

== Interrupt vectors ==
Some computer architectures still reserve the beginning of address space for other purposes, though; for instance, [[Intel]] [[x86]] systems reserve the first 256 double-words of address space for the [[interrupt vector table]] (IVT) if they run in [[real mode]].

A similar technique of using the zero page for hardware related vectors was employed in the ARM architecture. In badly written programs this could lead to "ofla" behaviour, where a program tries to read information from an unintended memory area, and treats executable code as data or vice versa. This is especially problematic if the zero page area is used to store system jump vectors and the firmware is tricked into overwriting them.<ref name="drobe_ofla"/>

== CP/M ==
{{Main|Zero page (CP/M)}}

In 8-bit [[CP/M]], the zero page is used for communication between the running program and the operating system.

== Page addressing ==
<!-- Note: The Intel 4004 had no zero page and did not support interrupts at all, but I parked this information here because it appears to be the most suitable place for now. This certainly needs to be reworded to put into a broader context. More research needed on behaviour on other processor types. -->
In some processor architectures, like that of the [[Intel 4004]] 4-bit processor, memory was divided into (256 byte) pages and special precautions had to be taken when the [[control flow]] crossed [[page boundary|page boundaries]], as some [[machine instruction]]s exhibited different behaviour if located in the last few instructions of a page, so that only few instructions were recommended to jump between pages.<ref name="Intel_1973_MCS-4"/>

== Null pointers ==
Contrary to the zero page's original preferential use, some modern operating systems such as [[FreeBSD]], [[Linux]], [[Oracle Solaris|Solaris]],  [[macOS]], and [[Microsoft Windows]]<ref name="msdn"/> actually make the zero page inaccessible to trap uses of [[null pointer]]s. Such pointer values may legitimately indicate uninitialized values or [[sentinel node]]s, but they do not point to valid objects. [[Software bug|Buggy code]] may try to access an object via a null pointer, and this can be trapped at the operating system level as a memory [[access violation]].

== See also ==
* [[Low memory]] – the first 64&nbsp;KB of memory (segment 0) in DOS
* [[Page boundary relocation]]

== References ==
{{Reflist|refs=
<ref name="Student Papers in Computer Architecture">{{cite book |last1=Sjödin |first1=Tomas |last2=Jonsson |first2=Johan |title=Student Papers in Computer Architecture |date=2006 |location=Umeå, Sweden |page=29 |s2cid=14355431 |url=http://pdfs.semanticscholar.org/fe94/c1e8319ee97d7649524e141a87ac2f5c8342.pdf |archive-url=https://web.archive.org/web/20190309043117/http://pdfs.semanticscholar.org/fe94/c1e8319ee97d7649524e141a87ac2f5c8342.pdf |url-status=dead |archive-date=2019-03-09 |access-date=2019-08-21}}</ref>
<ref name="msdn">{{cite web |title=Managing Virtual Memory |url=http://msdn.microsoft.com/en-us/library/ms810627.aspx |date=2014-12-05 |access-date=2014-12-05 |publisher=[[Microsoft]]}}</ref>
<ref name="drobe_ofla">{{cite web|title=ARM 'security hole' is ofla cousin |url=http://www.drobe.co.uk/article.php?id=1941 |date=2007-04-24 |access-date=2008-10-22 |publisher=drobe.co.uk}}</ref>
<ref name="Intel_1973_MCS-4">{{cite book |title=MCS-4 Assembly Language Programming Manual - The INTELLEC 4 Microcomputer System Programming Manual |chapter=4.1 Crossing Page Boundaries |edition=Preliminary |publisher=[[Intel Corporation]] |date=December 1973 |location=Santa Clara, California, USA |id=MCS-030-1273-1 |pages=((2-4, 2-14, 3-41, 4-1)) |url=http://bitsavers.trailing-edge.com/components/intel/MCS4/MCS-4_Assembly_Language_Programming_Manual_Dec73.pdf |access-date=2020-03-02 |url-status=live |archive-url=https://web.archive.org/web/20200301235541/http://bitsavers.trailing-edge.com/components/intel/MCS4/MCS-4_Assembly_Language_Programming_Manual_Dec73.pdf |archive-date=2020-03-01 |quote=[…] certain instructions function differently when located in the last byte (or bytes) of a page than when located elsewhere. […] Two addresses are on the same page if the highest order hexadecimal digit of their addresses are equal. […] If the JIN instruction is located in the last location of a page in memory, the highest 4 bits of the program counter are incremented by one, causing control to be transferred to the corresponding location on the next page. […] If […] the JIN had been located at address 255 decimal (0FF hexadecimai), control would have been transferred to address 115 hexadecimal, not 015 hexadecimal. This is dangerous programming practice, and should be avoided whenever possible. […] programs are held in either ROM or program RAM, both of which are divided into pages. Each page consists of 256 8-bit locations. Addresses 0 through 255 comprise the first page, 256-511 comprise the second page, and so on. In general, it is good programming practice to never allow program flow to cross a page boundary except by using a JUN or JMS instruction. […]}}</ref>
}}

== Further reading ==
* {{cite book |author-last1=Bray |author-first1=Andrew C. |author-last2=Dickens |author-first2=Adrian C. |author-last3=Holmes<!-- BA --> |author-first3=Mark A. |date=1983 |edition=3 |title=The Advanced User Guide for the BBC Microcomputer |publisher=The Cambridge Microcomputer Centre |isbn=0-946827-00-1}}
* {{cite magazine |author-first=Richard L. |author-last=Roth |title=Relocation Is Not Just Moving Programs |location=Ridgefield, CA, USA |magazine=[[Dr. Dobb's]] |publisher=[[People's Computer Company]] |id=#22 |volume=3 |number=2 |date=February 1978 |orig-year=1977 |pages=14–20<!-- in the issue --> (70–76<!-- in the volume -->) |isbn=0-8104-5490-4<!-- of the volume --> |url=https://archive.org/stream/dr_dobbs_journal_vol_03/dr_dobbs_journal_vol_03_djvu.txt |access-date=2019-04-19 |url-status=live |archive-url=https://web.archive.org/web/20190420010941/https://archive.org/stream/dr_dobbs_journal_vol_03/dr_dobbs_journal_vol_03_djvu.txt |archive-date=2019-04-20}}
* {{cite book |title=8086 Family Utilities - User's Guide for 8080/8085-Based Development Systems |chapter=1. Introduction: Segment Alignment |id=Order Number: 9800639-04 |edition=A620/5821 6K DD |version=Revision E |date=May 1982 |orig-year=1980, 1978 |publisher=[[Intel Corporation]] |location=Santa Clara, California, USA |page=1-6 |url=http://bitsavers.trailing-edge.com/pdf/intel/ISIS_II/9800639-04E_8086_Famility_Utilities_Users_Guide_May82.pdf |access-date=2020-02-29 |url-status=live |archive-url=https://web.archive.org/web/20200229032355/http://bitsavers.trailing-edge.com/pdf/intel/ISIS_II/9800639-04E_8086_Famility_Utilities_Users_Guide_May82.pdf |archive-date=2020-02-29}}

[[Category:Memory management]]