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Zilog Z80
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{{Short description|8-bit microprocessor}} {{Use mdy dates|date=May 2024}} {{Infobox CPU | name = Zilog Z80 | hide_subheadings = | image = Zilog Z80.jpg | alt = A close-up of a silver computer chip with a gold square on a white background. The chip has text on it that says "ZILOG Z80 CPU DALLAS 7623". | caption = A Z80 manufactured in June 1976 <!----------------- General Info -----------------> | produced-start = July 1976 | produced-end = June 2024 | soldby = [[Zilog]] | designfirm = [[Federico Faggin]], [[Masatoshi Shima]] | manuf1 = Zilog, [[Mostek]], [[Synertek]], [[Società Generale Semiconduttori|SGS]], [[NEC]], [[Sharp Corporation|Sharp]], [[Toshiba]], [[Rohm]], [[GoldStar]], [[Hitachi]], [[National Semiconductor]],{{efn|Only in CMOS, National made no NMOS version, according to Oral History with Federico Faggin}} and others | cpuid = <!-- CPUID or PVR value --> | code = <!-- numerical identifier for the CPU (product code) --> <!----------------- Performance ------------------> | slowest = 2.5 | fastest = 8 | slow-unit = MHz | fast-unit = MHz{{efn|CMOS variants went up to 20 MHz and binary compatible derivatives went up to 50 MHz}} | fsb-slowest = <!-- Slowest FSB speed --> | fsb-fastest = <!-- Fastest FSB speed --> | fsb-slow-unit = <!-- Unit for slow speed. Default: MHz --> | fsb-fast-unit = <!-- Unit for fast speed. Default: MHz --> | hypertransport-slowest = <!-- Slowest HyperTransport speed --> | hypertransport-fastest = <!-- Fastest HyperTransport speed --> | hypertransport-slow-unit = <!-- Unit for slow speed. Default: GT/s --> | hypertransport-fast-unit = <!-- Unit for fast speed. Default: GT/s --> | qpi-slowest = <!-- Slowest QPI (QuickPath Interconnect) speed --> | qpi-fastest = <!-- Fastest QPI speed --> | qpi-slow-unit = <!-- Unit for slow speed. Default: GT/s --> | qpi-fast-unit = <!-- Unit for fast speed. Default: GT/s --> | dmi-slowest = <!-- Slowest DMI (Direct Media Interface) speed --> | dmi-fastest = <!-- Fastest DMI speed --> | dmi-slow-unit = <!-- Unit for slow speed. Default: GT/s --> | dmi-fast-unit = <!-- Unit for fast speed. Default: GT/s --> | data-width = 8 bits<ref name="Zilog 2005" /> | address-width = 16 bits<ref name="Zilog 2005" /> | virtual-width = <!-- Virtual address bus width in bits --> <!-------------------- Cache ---------------------> | l1cache = <!-- Level 1 cache size --> | l2cache = <!-- Level 2 cache size --> | l3cache = <!-- Level 3 cache size --> | l4cache = <!-- Level 4 cache size --> | llcache = <!-- Last Level cache size --> <!------- Architecture and classification --------> | application = Embedded, desktop, handheld<!-- Handheld because it was used in the Game Boy and Game Gear devices. --> | size-from = [[4 μm process]]<!-- First fabrication size --> | size-to = <!-- Second fabrication size --> | microarch = <!-- Microarchitecture of the CPU --> | arch = Z80{{efn|Backwards compatible with Intel 8080}} | instructions = <!-- Instruction sets --> | extensions = <!-- Extensions to the instructions --> | numinstructions = <!-- Number of instructions --> <!----------- Physical specifications ------------> | transistors = 8,500 | numcores = <!-- Number of cores (2 for dual-core) --> | amountmemory = <!-- Amount of system RAM for SoC or SiP --> | gpu = <!-- Integrated GPU --> | co-processor = <!-- A [[co-processor]](s) used together --> | pack1 = 40-pin [[Dual in-line package|DIP]] | pack2 = 44-pin [[Plastic leaded chip carrier|PLCC]] | pack3 = 44-pin [[QFP]] | sock1 = <!-- (1..9) Names of the sockets that the CPU was made for --> <!--------- Products, models, variants -----------> | core1 = <!-- (1..9) Names of the cores --> | pcode1 = <!-- (1..9) Product code names --> | model1 = <!-- (1..9) Model names --> | brand1 = <!-- (1..9) Marketing names of the CPU --> | variant = <!-- Variants in the same family and generation --> <!------------------ History -------------------> | predecessor = [[Intel 8080]] | successor = {{hlist | [[Zilog Z180|Z180]] | [[Zilog Z280|Z280]] | [[Zilog eZ80|eZ80]] }} <!------------------ Support status -------------------> | support status = <!-- Current support status --> }} The '''Zilog Z80''' is an [[8-bit computing|8-bit]] microprocessor designed by [[Zilog]] that played an important role in the evolution of early personal computing. Launched in 1976, it was designed to be [[Backward compatibility|software-compatible]] with the [[Intel 8080]], offering a compelling alternative due to its better [[Integrated circuit|integration]] and increased performance. Along with the 8080's seven [[Processor register|registers]] and flags register, the Z80 introduced an alternate register set, two 16-bit index registers, and additional instructions, including [[bit manipulation]] and block copy/search. Originally intended for use in [[embedded system]]s like the 8080, the Z80's combination of compatibility, affordability, and superior performance led to widespread adoption in [[video game]] systems and [[home computer]]s throughout the late 1970s and early 1980s, helping to fuel the [[personal computing]] revolution. The Z80 was used in iconic products such as the [[Osborne 1]], [[TRS-80|Radio Shack TRS-80]], [[ColecoVision]], [[ZX Spectrum]], Sega's [[Master System]] and the ''[[Pac-Man]]'' arcade cabinet. In the early 1990s, it was used in portable devices, including the [[Game Gear]] and the [[TI-83 series]] of graphing calculators.<ref>{{Cite web |title=Chip Hall of Fame: Zilog Z80 Microprocessor - IEEE Spectrum |url=https://spectrum.ieee.org/chip-hall-of-fame-zilog-z80-microprocessor |access-date=2024-11-22 |website=spectrum.ieee.org |language=en}}</ref><ref>{{Cite web |last=Edwards |first=Benj |date=2024-04-22 |title=After 48 years, Zilog is killing the classic standalone Z80 microprocessor chip |url=https://arstechnica.com/gadgets/2024/04/after-48-years-zilog-is-killing-the-classic-standalone-z80-microprocessor-chip/ |access-date=2024-11-22 |website=Ars Technica |language=en-US}}</ref> The Z80 was the brainchild of [[Federico Faggin]], a key figure behind the creation of the Intel 8080. After leaving Intel in 1974, he co-founded Zilog with [[Ralph Ungermann]]. The Z80 debuted in July 1976, and its success allowed Zilog to establish its own [[Semiconductor fabrication plant|chip factories]].{{sfn|Faggin|Shima|Ungermann|2007}} For initial production, Zilog licensed the Z80 to U.S.-based [[Synertek]] and [[Mostek]], along with European [[second-source]] manufacturer, [[Società Generale Semiconduttori|SGS]]. The [[Semiconductor intellectual property core|design]] was also copied by various Japanese, Eastern European, and Soviet manufacturers gaining global market acceptance as major companies like [[NEC]], [[Toshiba]], [[Sharp Corporation|Sharp]], and [[Hitachi]] produced their own versions or compatible clones. Long after more advanced processors were introduced, the Z80 continued to be used in embedded systems, remaining in production until June 2024, nearly five decades after it began. Zilog also continued to enhance the basic design of the Z80 with several successors, including the [[Zilog Z180|Z180]], [[Zilog Z280|Z280]], and [[Zilog Z380|Z380]], with the latest iteration, the [[Zilog eZ80|eZ80]], introduced in 2001 and available for purchase {{as of|2025|lc=y}}.<ref name="discontinuation">{{Cite web |last=Edwards |first=Benj |date=April 22, 2024 |title=After 48 years, Zilog is killing the classic standalone Z80 microprocessor chip |url=https://arstechnica.com/gadgets/2024/04/after-48-years-zilog-is-killing-the-classic-standalone-z80-microprocessor-chip/ |access-date=May 23, 2024 |website=Ars Technica |language=en-us |archive-date=May 12, 2024 |archive-url=https://web.archive.org/web/20240512234211/https://arstechnica.com/gadgets/2024/04/after-48-years-zilog-is-killing-the-classic-standalone-z80-microprocessor-chip/ |url-status=live }}</ref> == History == [[File:Zilog Z-80 Microprocessor ad May 1976.jpg|thumb|upright=1.5|A May 1976 advertisement for the Z80 outlines its major advantages over the 8080.]] [[File:Z80-Z0840004PSC-HD.jpg|thumb|upright=1.5|Photo of the original Zilog Z80 [[microprocessor]] design in [[depletion-load nMOS]]. Total [[Die (integrated circuit)|die]] size is 3545×3350 μm. The blue squares around the outside are the pads that connect to the external pins. This chip was manufactured in 1990.]] [[File:Z84C0010FEC LQFP.png|thumb|A [[CMOS]] Z80 in a 44-pin [[quad flat package]].]] === Early history === At [[Fairchild Semiconductor]], and later at [[Intel]], [[physicist]] and [[engineer]] [[Federico Faggin]] had been working on fundamental [[transistor]] and [[semiconductor]] manufacturing technology. He also developed the basic design methodology used for memories and [[microprocessor]]s at Intel and led the work on the [[Intel 4004]], the [[Intel 8080]] and several other ICs. [[Masatoshi Shima]] was the principal logic and transistor-level designer of the 4004 and the 8080 under Faggin's supervision, while [[Ralph Ungermann]] was in charge of custom [[integrated circuit]] design.{{sfn|Faggin|Shima|Ungermann|2007|p=1}} In early 1974, Intel viewed microprocessors not so much as products to be sold on their own but as a way to sell more of its main products, [[static RAM]] and [[ROM]]. A reorganization placed some of the formerly independent sections under the direction of Les Vadasz, further diluting the microprocessor's place in the company. That year, the [[1973–1975 recession]] reached a peak, and Intel laid off several employees.{{sfn|Faggin|Shima|Ungermann|2007|p=1}} All of this led to Faggin becoming restless, and he invited Ungermann out for drinks and asked if he would be interested in starting their own company. Ungermann immediately agreed, and as he had less to do at Intel, he left in August or September, followed by Faggin, whose last day at Intel was Halloween 1974.{{sfn|Faggin|Shima|Ungermann|2007|p=2}} When Shima heard, he asked to come to the new company as well, but having no actual product design or money, they told him to wait.{{sfn|Faggin|Shima|Ungermann|2007|p=3}} The newly formed and unnamed company initially began designing a single-chip [[microcontroller]] called the 2001. They met with [[Synertek]] to discuss fabrication on their lines, and when Faggin began to understand the costs involved, it became clear that a low-cost product like this would not be able to compete with a design from a company with its own production lines, like Intel. They then began considering a more complex microprocessor instead, initially known as the Super 80, with the main feature being its use of a +5 V bus{{sfn|Faggin|Shima|Ungermann|2007|p=3}} instead of the more common −5, +5 and 12 V used by designs like the 8080. The new design was intended to be compatible with the 8080, but add a number of the features of the [[Motorola 6800]], including [[index register]]s and improved [[interrupt]]s.{{sfn|Faggin|Shima|Ungermann|2007|p=4}} === Exxon investment, detailed development begins === While still being set up, the industry newsletter ''Electronic News'' heard of them and published a story on the newly formed company. This attracted the attention of Exxon Enterprises, [[Exxon]]'s high-tech investment arm. At the time, in the midst of the recession, there was little [[venture capital]] available, with a total of $10 million for the entire industry being spent in all of 1975 (equivalent to ${{Inflation|US|10|1975}} million in {{Inflation/year|US}}). Someone from Exxon contacted the still-unnamed company,{{sfn|Faggin|Shima|Ungermann|2007|p=3}} and arranged a meeting that eventually led to them providing an initial $500,000 funding in June 1975 (equivalent to ${{Inflation|US|0.5|1975|r=1}} million in {{Inflation/year|US}}).{{sfn|Faggin|Shima|Ungermann|2007|p=8}} With funding being discussed and a design to be built, Shima joined in February 1975.{{sfn|Faggin|Shima|Ungermann|2007|p=4}} Shima immediately set about producing a high-level design, adding several concepts of his own. In particular, he used his experience on [[NEC]] [[minicomputer]]s to add the concept of two sets of [[processor register]]s so they could quickly respond to [[interrupt]]s.{{sfn|Faggin|Shima|Ungermann|2007|p=2}}{{efn|This was a fairly common feature of minicomputer designs of the era, and found its way into a number of early microprocessors.}} Ungerman began the development of a series of related controllers and peripheral chips that would complement the design.{{sfn|Faggin|Shima|Ungermann|2007|p=5}} Through this period, Shima developed a legendary reputation for being able to convert logic concepts into physical design in realtime; while discussing a proposed feature, he would often interrupt and state how much room that would take on the chip and veto its addition if it was too large.{{sfn|Faggin|Shima|Ungermann|2007|p=19}} The first pass at the design was complete by April 1975. Shima had completed a logic layout by the beginning of May. A second version of the logic design was issued on August 7 and the bus details by September 16. Tape-out was completed in November and converting the tape into a production mask required two more months.{{sfn|Faggin|Shima|Ungermann|2007|p=6}} Faggin had already started looking for a production partner. By this time, Synertek and [[Mostek]] had both set up the depletion-mode production lines that could be used to produce the design. Having talked to Synertek previously, Faggin approached them first. However, the president of Synertek demanded that the company be given a [[second source]] license, allowing them to sell the design directly. Faggin thought this would mean they could never compete even if they set up their own lines, and the agreement fell through. He then turned to Mostek, who agreed to a term of exclusivity while Zilog got their lines set up, and was eventually given the second source agreement.{{sfn|Faggin|Shima|Ungermann|2007|p=7}} After considering multiple names for the new company, and finding them so unmemorable they could not recall them even a day later, Faggin and Ungermann were kicking around ideas based on "integrated logic" when Ungermann said, "How about Zilog?" Faggin immediately agreed, stating they could say it was the "last word in integrated logic". When they met the next day and both immediately recalled it, the company had its name.{{sfn|Faggin|Shima|Ungermann|2007|p=17}} === Into production === The first samples were returned from Mostek on March 9, 1976.{{sfn|Faggin|Shima|Ungermann|2007|p=5}} By the end of the month, they had also completed an [[assembler (computing)|assembler]]-based [[microprocessor development board|development system]]. Some of the Z80 support and peripheral ICs were under development at this point, and some of them were launched during the following year. Among them were the Z80 CTC (counter/timer), Z80 DMA<ref>{{Cite web |title=Z80® DMA Direct Memory Access Controller |url=http://www.bitsavers.org/components/zilog/z80/Z80_DMA_Product_Specification_Feb80.pdf |access-date=January 8, 2024 |archive-date=February 5, 2024 |archive-url=https://web.archive.org/web/20240205070618/http://www.bitsavers.org/components/zilog/z80/Z80_DMA_Product_Specification_Feb80.pdf |url-status=live }}</ref> (direct memory access), Z80 DART (dual asynchronous receiver–transmitter), Z80 SIO (synchronous communication controller), and Z80 PIO (parallel input/output). The Z80 was officially launched in July 1976.{{sfnp|Anderson|1994|p=51}} One of the first customers was a buyer who, unknown to Zilog, worked for NEC. At the time, the Japanese electronics companies were well known for taking US chip designs and producing them without a license. The Zilog team had worried about this, and Faggin had come up with the idea of adding transistors that would be subtly modified to operate differently than a visual inspection would suggest. Shima added six of these "traps" around the design. Sometime later, Shima was told by an engineer within NEC that the traps had delayed their copying efforts by six months.{{sfn|Faggin|Shima|Ungermann|2007|p=13}} The launch allowed Faggin and Ungermann to approach Exxon looking for funding to build their own fab. The company agreed, and Zilog built a production line. This allowed them to capture about 60 to 70% of the total market for Z80 sales.{{sfn|Faggin|Shima|Ungermann|2007|p=9}} With their own line running, Mostek was given the go-ahead to start sales of their version, the MK3880, which provided a [[second source]] for customers that Intel lacked. At the time, a second source was considered extremely important as a start-up like Zilog might go out of business and leave potential customers stranded.{{sfn|Faggin|Shima|Ungermann|2007|p=4}}{{efn|Zilog manufactured the Z80 as well as most of their other products for many years until they sold their [[manufacturing plant]]s and become the "[[fabless]]" company they are today.}} === Comparison with the 8080 === Faggin designed the [[instruction set]] to be [[binary-code compatibility|binary compatible]] with the 8080{{sfnp|Anderson|1994|p=57}}<ref name="Brock 2003">{{Cite book |last=Brock |first=Gerald W. |url=https://archive.org/details/secondinformatio0000broc |title=The second information revolution |date=2003 |publisher=Harvard University Press |isbn=978-0-674-01178-6 |url-access=registration}}</ref> so that most 8080 code, notably the [[CP/M]] [[operating system]] and Intel's [[PL/M]] compiler for 8080 (as well as its generated code), would run unmodified on the new Z80 CPU. Masatoshi Shima designed most of the [[microarchitecture]] as well as the gate and transistor levels of the Z80 CPU, assisted by a small number of engineers and [[integrated circuit layout|layout]] people.<ref>{{Cite magazine |date=November 29, 1982 |title=History of the 8-bit: travelling far in a short time |url=https://books.google.com/books?id=HjAEAAAAMBAJ&pg=PA58 |url-status=live |archive-url=https://web.archive.org/web/20240105080752/https://books.google.com/books?id=HjAEAAAAMBAJ&pg=PA58 |archive-date=January 5, 2024 |magazine=[[InfoWorld]] |publisher=Popular Computing Inc. |location=Palo Alto, CA |pages=58–60 |volume=4 |issue=47 |issn=0199-6649}}</ref><ref>{{Cite magazine |last1=Faggin |first1=Federico |last2=Shima |first2=Masatoshi |author-link2=Masatoshi Shima |last3=Ungermann |first3=Ralph |date=August 19, 1976 |title=Z-80 chip set heralds third microprocessor generation |url=https://www.worldradiohistory.com/Archive-Electronics/70s/76/Electronics-1976-08-19.pdf#page=91 |url-status=live |archive-url=https://web.archive.org/web/20230131151012/https://worldradiohistory.com/Archive-Electronics/70s/76/Electronics-1976-08-19.pdf#page=91 |archive-date=January 31, 2023 |magazine=[[Electronics (magazine)|Electronics]] |publisher=[[McGraw Hill Education|McGraw–Hill]] |location=New York |pages=89–93 |volume=49 |issue=17}}</ref> CEO Federico Faggin was actually heavily involved in the chip layout work, together with two dedicated layout people. According to Faggin, he worked 80 hours a week in order to meet the tight schedule given by the financial investors.{{sfn|Faggin|Shima|Ungermann|2007}} The Z80 offered multiple improvements over the 8080:<ref name="Brock 2003" /> * An enhanced [[instruction set]] including: ** a more logical, comprehensible and readable system of assembler instruction [[Assembly language#Opcode mnemonics and extended mnemonics|mnemonics]] ** more flexible 16-bit data movement (load, or LD) instructions, crucially including the stack pointer SP ** more flexible addressing modes for input/output to external peripheral ports ** single-bit addressing of all registers and memory, including bit testing ** shifts/rotates on memory and registers other than the [[accumulator (computing)|accumulator]] ** improved and more accurate (than the previous 8080) [[binary-coded decimal|BCD]] arithmetic ** rotate instructions for BCD number strings in memory ** 16-bit subtraction and 8-bit negation ** [[program loop]]ing ** program counter (PC) relative jumps ** [[block move|block copy]], block [[input/output]] (I/O), and byte search instructions.{{sfnp|Ciarcia|1981|pp=31, 32}} * An [[overflow flag]] with better support for signed 8- and 16-bit arithmetics.{{efn|Although the 8080 had 16-bit addition and 16-bit [[Increment and decrement operators|increment and decrement instructions]], it had no explicit 16-bit subtraction, and no overflow flag. The Z80 complemented this with the ADC HL,rr and SBC HL,rr instructions, which sets the new overflow flag accordingly. (The 8080-compatible ADD HL,rr does not.)}} * New IX and IY [[index register]]s with instructions for direct ''base+[[Offset (computer science)|offset]]'' addressing * A better [[interrupt]] system: ** A more automatic and general [[Interrupt vector|vectorized interrupt system]], ''mode 2'', primarily intended for Zilog's line of counter/timers, DMA and communications controllers, as well as a fixed vector interrupt system, ''mode 1'', for simple systems with minimal hardware (with ''mode 0'' being the 8080-compatible mode).<ref name="Wai-Kai 2002">{{Cite book |last=Chen |first=Wai-Kai |title=The circuits and filters handbook |date=2002 |publisher=[[CRC Press]] |isbn=978-0-8493-0912-0 |page=1943 |quote=interrupt processing commences according to the interrupt method stipulated by the IM ''i'', ''i'' = 0, 1, or 2, instruction. If ''i'' = 1, for direct method, the PC is loaded with 0038H. If ''i'' = 0, for vectored method, the interrupting device has the opportunity to place the op-code for one byte. If ''i'' = 2, for indirect vector method, the interrupting device must then place a byte. The Z80 then uses this byte where one of 128 interrupt vectors can be selected by the byte.}}</ref> ** A non-maskable interrupt (NMI), which can be used to respond to power-down situations or other high-priority events (and allowing a minimalistic Z80 system to easily implement a two-level interrupt scheme in ''mode 1''). * A complete duplicate [[register file]],<ref>{{Cite book |last=Mathur |title=Introduction to Microprocessors |date=1989 |publisher=Tata McGraw-Hill Publishing Company |isbn=978-0-07-460222-5 |page=111 |quote=The register architecture of the Z80 is more innovative than that of the 8085}}</ref> which could be quickly switched, to speed up response to [[interrupt]]s such as fast asynchronous event handlers or a [[multitasking (computing)|multitasking]] [[scheduler (computing)|dispatcher]]. Although they were not intended as extra registers for general code, they were nevertheless used that way in some applications.{{efn|Notably to simultaneously handle the 32-bit [[significand|mantissas]] of two [[operand]]s in the 40-bit [[floating-point arithmetic|floating-point]] format used in the [[ZX81]] home computer. They were also used in a similar fashion in some earlier but lesser known Z80-based computers, such as the Swedish [[ABC 80]] and [[ABC 800]].}} * Less hardware required for [[power supply]], clock generation and interface to memory and I/O * Single 5-volt power supply (the 8080 needed −5 V, +5 V, and +12 V). * Single-phase 5-volt clock (the 8080 needed a high-amplitude (9 to 12 volts) non-overlapping [[two-phase clock]]). * Built-in [[DRAM]] [[memory refresh|refresh]], which would otherwise require external circuitry, unless SRAM, more expensive and less dense (but faster), was used.{{efn|As this refresh does not need to transfer any data, just output sequential row-addresses, it occupies less than 1.5 T-states. The dedicated M1-signal (''machine cycle one'') in the Z80 can be used to allow memory chips the same amount of access time for instruction fetches as for data access, i.e almost 2 full T-states out of the 4T ''fetch'' cycle (as well as out of the 3T data ''read'' cycle). The Z80 could use memory with the same range of access times as the 8080 (or the 8086) at the same clock frequency. This long M1-signal (relative to the clock) also meant that the Z80 could employ about 4–5 times the internal frequency of a 6800, 6502 or similar using the same type of memory.}} * Non-multiplexed buses (the 8080 had state signals multiplexed onto the data bus). * A special reset that zeroes only the program counter, so that a single Z80 CPU could be used in a development system such as an [[in-circuit emulator]].<ref>{{Cite web |last=Brewer |first=Tony |title=Z80 Special Reset |website=[[GitHub]] |url=https://github.com/redcode/Z80/wiki/Z80-Special-Reset |access-date=April 27, 2024 |archive-date=April 27, 2024 |archive-url=https://web.archive.org/web/20240427180745/https://github.com/redcode/Z80/wiki/Z80-Special-Reset |url-status=live }}</ref> === Success in the market === The Z80 took over from the 8080 and its offspring, the [[Intel 8085|8085]], in the processor market<ref>{{Cite web |last=Adrian |first=Andre |date=June 4, 2011 |title=Z80, the 8-bit Number Cruncher |url=http://www.andreadrian.de/oldcpu/Z80_number_cruncher.html |url-status=live |archive-url=https://web.archive.org/web/20231126092639/http://www.andreadrian.de/oldcpu/Z80_number_cruncher.html |archive-date=November 26, 2023}}</ref> and became one of the most popular and widely used 8-bit CPUs.<ref name="Balch 2003"/><ref name="Seybold 1983" /> Some organizations such as [[BT Group|British Telecom]] remained loyal to the 8085 for embedded applications, owing to their familiarity with it and to its on-chip serial interface and interrupt architecture. Likewise, [[Zenith Data Systems]] paired the 8085 with the 16-bit [[Intel 8088]] in its first MS-DOS computer, the [[Zenith Z-100]], despite having previous experience with its pioneering Z80-based [[Zenith Z-89|Heathkit H89 and Zenith Z-89]] products. However, other computers were made integrating the Z80 with other CPUs: the Radio Shack [[TRS-80 Model II#Model 16|TRS-80 Model 16]] with a [[Motorola 68000]], the [[Rainbow 100|DEC Rainbow]] with an 8088, and the [[Commodore 128]] with a [[MOS Technology 8502]]. Zilog was later producing a low-power Z80 suitable for the growing laptop computer market of the early 1980s. Intel produced a CMOS 8085 (80C85) used in battery-powered portable computers, such as the [[Kyocera]]-designed laptop from April 1983, also sold by Tandy (as [[TRS-80 Model 100]]), Olivetti, and NEC. In following years, however, CMOS versions of the Z80 (from both Zilog and Japanese manufacturers) would dominate this market as well, in products such as the [[Amstrad NC100]], [[Cambridge Z88]] and Tandy's own WP-2. Perhaps a key to the initial success of the Z80 was the built-in DRAM refresh, at least in markets such as [[CP/M]] and other office and home computers. (Most Z80 [[embedded system]]s use [[Static random-access memory|static RAM]] that do not need refresh.) It may also have been its minimalistic two-level interrupt system, or conversely, its general multi-level daisy-chain interrupt system useful in servicing multiple Z80 IO chips. These features allowed systems to be built with less support hardware and simpler circuit board layouts. However, others claim that its popularity was due to the duplicated registers that allowed fast context switches or more efficient processing of things like floating-point math compared to 8-bit CPUs with fewer registers. (The Z80 can keep several such numbers internally, using HL'HL, DE'DE and BC'BC as 32-bits registers, avoiding having to access them from slower RAM during computation.)<ref>{{Cite web |last=Adrian |first=Andre |date=June 4, 2011 |title=Z80, the 8-bit Number Cruncher: Z80 32-bit (long) add |url=http://www.andreadrian.de/oldcpu/Z80_number_cruncher.html#mozTocId228550 |url-status=live |archive-url=https://web.archive.org/web/20231126092639/http://www.andreadrian.de/oldcpu/Z80_number_cruncher.html#mozTocId228550 |archive-date=November 26, 2023}}</ref> For the original [[NMOS logic|NMOS]] design, the specified upper clock-frequency limit increased successively from the introductory 2.5 [[Hertz#SI multiples|MHz]], via the well known 4 MHz (Z80A), up to 6 MHz (Z80B) and 8 MHz (Z80H).<ref>{{Cite book |title=Popular Computing |date=1983 |publisher=[[McGraw Hill Education|McGraw-Hill]] |page=15}}</ref><ref>{{Cite magazine |last=Markoff |first=John |date=October 18, 1982 |title=Zilog's speedy Z80 soups up 8-bit to 16-bit performance |url=https://books.google.com/books?id=CjAEAAAAMBAJ&pg=PA1 |url-status=live |archive-url=https://web.archive.org/web/20240105083032/https://books.google.dk/books?id=CjAEAAAAMBAJ&pg=PA1 |archive-date=January 5, 2024 |magazine=[[InfoWorld]] |publisher=Popular Computing, Inc. |location=Palo Alto, CA |page=1 |volume=4 |issue=41 |issn=0199-6649}}</ref> An NMOS version was produced as a 10 MHz part beginning in the late 1980s. [[CMOS]] versions were developed with specified upper frequency limits ranging from 4 MHz up to 20 MHz for the version sold today. The CMOS versions allowed low-power standby with internal state retained, having no ''lower'' frequency limit.{{efn|Unlike the original nMOS version, which used dynamic latches and could not be stopped for more than a few thousand clock cycles.}} The fully compatible derivatives [[Hitachi HD64180|HD64180]]/[[Zilog Z180|Z180]]<ref>{{Cite book |title=Electronic design |date=1988 |publisher=Hayden |page=142 |quote=In addition to supporting the entire Z80 instruction set, the Z180}}</ref><ref>{{Cite web |last=Ganssle |first=Jack G. |date=1992 |title=The Z80 Lives! |url=http://www.z80.info/z80lives.htm |url-status=live |archive-url=https://web.archive.org/web/20231220144616/http://www.z80.info/z80lives.htm |archive-date=December 20, 2023 |quote=The designers picked an architecture compatible with the Z80, giving Z80 users a completely software compatible upgrade path. The 64180 processor runs every Z80 instruction exactly as a Z80 does}}</ref> and [[Zilog eZ80|eZ80]] are currently specified for up to 33 MHz and 50 MHz, respectively. == Design == {{More citations needed section|date=February 2025}} === Programming model and register set === [[File:Z80 arch.svg|thumb|upright=1.95|An approximate block diagram of the Z80: There is no dedicated adder for offsets or separate incrementer for R, and no need for more than a single 16-bit temporary register WZ (although the incrementer latches are also used as a 16-bit temporary register, in other contexts). It is the PC and IR registers that are placed in a separate group, with a detachable bus segment, to allow updates of these registers in parallel with the main register bank.<ref>{{Cite web |last=Shiriff |first=Ken |title=Down to the silicon: how the Z80's registers are implemented |url=https://www.righto.com/2014/10/how-z80s-registers-are-implemented-down.html |url-status=live |archive-url=https://web.archive.org/web/20231105135940/http://www.righto.com/2014/10/how-z80s-registers-are-implemented-down.html |archive-date=November 5, 2023}}</ref>]] The programming model and register set of the Z80 are fairly conventional, ultimately based on the register structure of the [[Datapoint 2200]]. The Z80 was designed as an extension of the Intel 8080, created by the same engineers, which in turn was an extension of the [[Intel 8008|8008]]. The 8008 was basically a [[PMOS logic|PMOS]] implementation of the TTL-based CPU of the Datapoint 2200.{{efn|The related [[Intel 8086|8086]] family also inherited this register design.}} The 2200 design allowed 8-bit registers H and L (High and Low) to be paired into a 16-bit address register HL.{{efn|This variable HL pointer was actually the only way to access memory (for data) in the Datapoint 2200, and hence also in the Intel 8008. No direct addresses could be used to access data.}} In the 8080, this pairing was added to the BC and DE pairs as well, while HL was generalized to allow use as a 16-bit accumulator, not just an address register. The 8080 also introduced immediate 16-bit data for BC, DE, HL, and SP loads. Furthermore, direct 16-bit copying between HL and memory was now possible, using a direct address. The Z80 [[Orthogonal instruction set|orthogonalized]] this further by making all 16-bit register pairs, including IX and IY, more general purpose, as well as allowing 16-bit copying directly to and from memory for all of these pairs. The 16-bit IX and IY registers in the Z80 are primarily intended as base address-registers, where a particular instruction supplies a constant offset that is added to the previous values, but they are also usable as 16-bit accumulators, among other things. A limitation is that all operand references involving IX or IY require an extra instruction prefix byte, adding at least four clock cycles over the timing of an instruction using HL instead; this sometimes makes using IX or IY less efficient than a method using only the 8080-model registers. The Z80 also introduced a new signed [[overflow flag]] and complemented the fairly simple 16-bit arithmetics of the 8080 with dedicated instructions for ''signed'' 16-bit arithmetics.[[File:Z80 pinout.svg|thumb|upright=1.5|The Z80's original [[dual in-line package|DIP40]] chip package pinout]]The 8080-compatible registers AF, BC, DE, HL are duplicated as a separate register file in the Z80,<ref>{{Cite book |title=Kilobaud |date=1977 |publisher=1001001 |page=22}}</ref> where the processor can quickly (in four t-states, the least possible execution time for any Z80 instruction) switch from one bank to the other;<ref>{{Cite book |last=Zaks |first=Rodnay |url=https://archive.org/details/Programming_The_Z80_Third_Edition_Rodnay_Zaks/ |title=Programming the Z80 |date=1982 |publisher=SYBEX |isbn=978-0-89588-069-7 |edition=3rd |page=62}}</ref> a feature useful for speeding up responses to single-level, high-priority interrupts. The dual register-set is useful in the embedded role, as it improves interrupt handling performance, but found widespread use in the personal computer role as an additional set of general registers for complex code like [[floating-point arithmetic]] or home computer games. The duplicate register file is often referred to as the "alternate register set" (by some, the "primed" register file since the apostrophe character is used to denote them in assembler source code and the Zilog documentation). This emphasizes that only one set is addressable at any time. However, the 8-bit accumulator A with its flag register F is bifurcated from the "general purpose" register pairs HL, DE and BC. This is accomplished with two separate instructions used to swap their accessibilities: <code>EX AF,AF'</code> exchanges only register pair AF with AF', while the <code>EXX</code> instruction exchanges the three general purpose register pairs HL, DE and BC with their alternates HL', DE' and BC'. Thus the accumulator A can interact independently with any of the general purpose 8-bit registers in the alternate (or primed) register file, or, if HL' contains a pointer to memory, some byte there (DE' and BC' can also transfer 8-bit data between memory and accumulator A). This can become confusing for programmers because after executing <code>EX AF,AF'</code> or <code>EXX</code>, the contents of the alternate (primed) registers are now in the main registers, and vice versa. The only way for the programmer to understand and track this swapped condition is to trace through the code flow, noting each occurrence of a register swap instruction. Obviously if jump and call instructions are made within these code segments it can quickly become difficult to tell which register file is in context unless carefully commented. Thus it is advisable that exchange instructions be used directly and in short discrete code segments. The Zilog Z280 instruction set includes <code>JAF</code> and <code>JAR</code> instructions which jump to a destination address if the alternate registers are in context (thus officially recognizing this programming complication). ==== Registers ==== {| class="floatright" style="font-size:88%; border: 1px solid #a2a9b1;" |+ '''Zilog Z80 registers''' |- | {| style="font-size:88%;" |- | style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>4</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>3</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub> | style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub> | style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub> | style="width:auto;" | ''(bit position)'' |- |colspan="17" | '''Main registers''' |- style="background:silver;color:black" | style="text-align:center;" colspan="8"| Accumulator (A) | style="text-align:center;background:#DDD" colspan="8"| Flags (F) | style="background:white; color:black;"| '''AF''' |- style="background:silver;color:black" | style="text-align:center;" colspan="8"| B | style="text-align:center;" colspan="8"| C | style="background:white; color:black;"| '''BC''' |- style="background:silver;color:black" | style="text-align:center;" colspan="8"| D | style="text-align:center;" colspan="8"| E | style="background:white; color:black;"| '''DE''' |- style="background:silver;color:black" | style="text-align:center;" colspan="8"| H | style="text-align:center;" colspan="8"| L | style="background:white; color:black;"| '''HL''' |- |colspan="17" | '''Alternate (shadow) registers''' |- style="background:silver;color:black" | style="text-align:center;" colspan="8"| Accumulator' (A') | style="text-align:center;background:#DDD" colspan="8"| Flags' (F') | style="background:white; color:black;"| '''AF{{'}}''' |- style="background:silver;color:black" | style="text-align:center;" colspan="8"| B' | style="text-align:center;" colspan="8"| C' | style="background:white; color:black;"| '''BC{{'}}''' |- style="background:silver;color:black" | style="text-align:center;" colspan="8"| D' | style="text-align:center;" colspan="8"| E' | style="background:white; color:black;"| '''DE{{'}}''' |- style="background:silver;color:black" | style="text-align:center;" colspan="8"| H' | style="text-align:center;" colspan="8"| L' | style="background:white; color:black;"| '''HL{{'}}''' |- |colspan="17" | '''Index registers''' |- style="background:silver;color:black" | style="text-align:center;" colspan="16"| Index X | style="background:white; color:black;"| '''IX''' |- style="background:silver;color:black" | style="text-align:center;" colspan="16"| Index Y | style="background:white; color:black;"| '''IY''' |- style="background:silver;color:black" | style="text-align:center;" colspan="16"| Stack Pointer | style="background:white; color:black;"| '''SP''' |- |colspan="17" | '''Other registers''' |- style="background:silver;color:black" | style="text-align:center;" colspan="8"| Interrupt vector | style="text-align:center;" colspan="8"| Refresh counter | style="background:white; color:black;"| '''I/R''' |- |colspan="17" | '''Program counter''' |- style="background:silver;color:black" | style="text-align:center;" colspan="16"| Program Counter | style="background:white; color:black;"| '''PC''' |- |colspan="17" | '''Status register''' |- style="background:silver;color:black" | style="background:white; color:black;" colspan="8"| <!--NEED TO ADD INTERRUPT STATUS/MODE BITS--> | style="text-align:center;"| [[Sign flag|S]] | style="text-align:center;"| [[Zero flag|Z]] | style="text-align:center;"| - | style="text-align:center;"| [[Adjust flag|H]] | style="text-align:center;"| - | style="text-align:center;"| [[Parity flag|P]]/[[Overflow flag|V]] | style="text-align:center;"| N | style="text-align:center;"| [[Carry flag|C]] | style="background:white; color:black" | '''F'''lags |} |} As on the 8080, 8-bit registers are typically paired to provide 16-bit versions. The 8080 compatible registers<ref name="Heath 2003">{{Cite book |last=Heath |first=Steve |url=https://archive.org/details/embeddedsystemsd0000heat |title=Embedded systems design |date=2003 |publisher=Newnes |isbn=978-0-7506-5546-0 |location=Oxford |page=21 |url-access=registration}}</ref> are: * <code>AF</code>: 8-bit [[Accumulator (computing)|accumulator]] (A) and flag bits (F) carry, zero, minus, parity/overflow, half-carry (used for [[Binary-coded decimal|BCD]]), and an Add/Subtract flag (usually called N) also for BCD * <code>BC</code>: 16-bit data/address register or two 8-bit registers * <code>DE</code>: 16-bit data/address register or two 8-bit registers * <code>HL</code>: 16-bit accumulator/address register or two 8-bit registers * <code>SP</code>: [[stack pointer]], 16 bits * <code>PC</code>: program counter, 16 bits The new registers introduced with the Z80 are: * <code>IX</code>: 16-bit index or base register for 8-bit immediate offsets * <code>IY</code>: 16-bit index or base register for 8-bit immediate offsets * <code>I</code>: interrupt vector base register, 8 bits * <code>R</code>: DRAM refresh counter, 8 bits ([[Most significant bit|msb]] does not count) * <code>AF'</code>: alternate (or shadow) accumulator and flags (''toggled in and out with EX AF,AF' '') * <code>BC'</code>, <code>DE'</code> and <code>HL'</code>: alternate (or shadow) registers (''toggled in and out with EXX'') * Four bits of interrupt status and interrupt mode status The ''refresh register'', <code>R</code>, increments each time the CPU fetches an opcode (or an opcode prefix, which internally executes like a 1-byte instruction) and has no simple relationship with program execution. This has sometimes been used to generate [[pseudorandom]] numbers in games, and also in software protection schemes.{{Citation needed|date=February 2012}} It has also been employed as a "hardware" counter in some designs; an example of this is the [[ZX81]], which lets it keep track of character positions on the TV screen by triggering an interrupt at [[integer overflow|wrap around]] (by connecting INT to A6). The ''interrupt vector register'', <code>I</code>, is used for the Z80 specific mode 2 interrupts (selected by the <code>IM 2</code> instruction). It supplies the high byte of the base address for a 128-entry table of [[interrupt service routine|service routine]] addresses which are selected via an index sent to the CPU during an [[interrupt]] acknowledge cycle; this index is simply the low byte part of the pointer to the tabulated indirect address pointing to the service routine.<ref name="Wai-Kai 2002" /> The pointer identifies a particular peripheral chip or peripheral function or event, where the chips are normally connected in a so-called [[Daisy chain (electrical engineering)|daisy chain]] for priority resolution. Like the refresh register, this register has also sometimes been used creatively; in interrupt modes 0 and 1 (or in a system not using interrupts) it can be used as simply another 8-bit data register. The instructions <code>LD A,R</code> and <code>LD A,I</code> affect the Z80 flags register, unlike all the other <code>LD</code> (load) instructions. The Sign (bit 7) and Zero (bit 6) flags are set according to the data loaded from the Refresh or Interrupt source registers. For both instructions, the Parity/Overflow flag (bit 2) is set according to the current state of the IFF2 flip-flop.<ref>{{Cite web |last=Rison |first=Mark |editor-last=Young |editor-first=Sean |title=Z80 Flag Affection |url=http://www.z80.info/z80sflag.htm |url-status=live |archive-url=https://web.archive.org/web/20231223185036/http://z80.info/z80sflag.htm |archive-date=December 23, 2023 |access-date=June 14, 2016 |website=z80.info |publisher=Thomas Scherrer}}</ref> ==== Microarchitecture ==== Although the Z80 is generally considered an eight-bit CPU, it has a four-bit [[Arithmetic logic unit|ALU]], so calculations are done in two steps.<ref>{{Cite web |last=Shirriff |first=Ken |title=The Z-80 has a 4-bit ALU. Here's how it works. |url=http://www.righto.com/2013/09/the-z-80-has-4-bit-alu-heres-how-it.html |archive-url=https://web.archive.org/web/20130909224112/http://www.righto.com/2013/09/the-z-80-has-4-bit-alu-heres-how-it.html |archive-date=September 9, 2013 |access-date=November 16, 2021}}</ref> === Z80 assembly language === ==== Datapoint 2200 and Intel 8008 ==== The first Intel 8008 [[assembly language]] was based on a simple (but systematic) syntax inherited from the Datapoint 2200 design. This original syntax was later transformed into a new, somewhat more traditional, assembly language form for this same original 8008 chip. At about the same time, the new assembly language was also extended to accommodate the additional addressing modes in the more advanced Intel 8080 chip (the 8008 and 8080 shared a language subset without being [[binary-code compatibility|binary compatible]]; however, the 8008 was binary compatible with the Datapoint 2200). In this process, the mnemonic <code>L</code>, for ''LOAD'', was replaced by various abbreviations of the words ''LOAD'', ''STORE'' and ''MOVE'', intermixed with other symbolic letters. The mnemonic letter <code>M</code>, for ''memory'' (referenced by HL), was lifted out from within the instruction mnemonic to become a syntactically freestanding ''operand'', while registers and combinations of registers became inconsistently denoted; either by abbreviated operands (MVI D, LXI H and so on), within the instruction mnemonic itself (LDA, LHLD and so on), or both at the same time (LDAX B, STAX D and so on). {| class="wikitable" |- ! Intel 8008<br />Datapoint 2200 ! Intel 8080<br />Intel 8085 ! Zilog Z80 ! Intel 8086/<br />Intel 8088 |- ! <small>before ca. 1973</small> ! <small>ca. 1974</small> ! <small>1976</small> ! <small>1978</small> |- | <syntaxhighlight lang="nasm" inline>LBC</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV B,C</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD B,C</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV CH,CL</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LDAX B</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD A,(BC)</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>LAM</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV A,M</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD A,(HL)</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV AL,[BX]</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>LBM</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV B,M</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD B,(HL)</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV CH,[BX]</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>STAX D</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD (DE),A</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>LMA</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV M,A</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD (HL),A</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV [BX],AL</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>LMC</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV M,C</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD (HL),C</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV [BX],CL</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>LDI 56</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MVI D,56</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD D,56</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV DL,56</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>LMI 56</syntaxhighlight>{{efn|Load memory immediate not available on Datapoint 2200.}} | <syntaxhighlight lang="nasm" inline>MVI M,56</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD (HL),56</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV byte ptr [BX],56</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LDA 1234</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD A,(1234)</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV AL,[1234]</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>STA 1234</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD (1234),A</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV [1234],AL</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD B,(IX+56)</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV CH,[SI+56]</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD (IX+56),C</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV [SI+56],CL</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD (IY+56),78</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV byte ptr [DI+56],78</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LXI B,1234</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD BC,1234</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV CX,1234</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LXI H,1234</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD HL,1234</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV BX,1234</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>SHLD 1234</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD (1234),HL</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV [1234],BX</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LHLD 1234</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD HL,(1234)</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV BX,[1234]</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD BC,(1234)</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV CX,[1234]</syntaxhighlight> |- | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>--</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>LD IX,(1234)</syntaxhighlight> | <syntaxhighlight lang="nasm" inline>MOV SI,[1234]</syntaxhighlight> |}''Illustration of four syntaxes, using samples of equivalent, or (for 8086) very similar, load and store instructions.<ref name="Durda 2012">{{Cite web |last=Durda IV |first=Frank |date=2012 |title=8080/Z80 Instruction Set |url=http://nemesis.lonestar.org/computers/tandy/software/apps/m4/qd/opcodes.html |url-status=dead |archive-url=https://web.archive.org/web/20160211094642/http://nemesis.lonestar.org/computers/tandy/software/apps/m4/qd/opcodes.html |archive-date=February 11, 2016 |access-date=July 22, 2009}}</ref> The Z80 syntax uses parentheses around an expression to indicate that the value should be used as a memory address (as mentioned below), while the 8086 syntax uses brackets instead of ordinary parentheses for this purpose. Both Z80 and 8086 use the + sign to indicate that a constant is added to a base register to form an address. Note that the 8086 is not a complete superset of the Z80. BX is the only 8086 register pair that can be used as a pointer.'' ==== New syntax ==== Because Intel claimed a copyright on their assembly mnemonics,<ref>{{Cite book |title=Intel Component Data Catalog 1978 |date=1978 |publisher=Intel Corporation |location=Santa Clara, CA |pages=11–17 |chapter=8080A/ 8-Bit N-Channel Microprocessor |quote=All mnemonics copyright Intel Corporation 1977}}</ref> a new assembly syntax had to be developed for the Z80. This time a more systematic approach was used: * All registers and register pairs are explicitly denoted by their full names * Parentheses are consistently used to indicate "memory contents at" (constant address or variable pointer dereferencing) with the exception the jump instructions <code>JP (HL)</code>, <code>JP (IX)</code>, and <code>JP (IY)</code>. These load the new PC address from the respective register directly, without indirecting through memory.{{efn|Jump (<code>JP</code>) instructions, which load the program counter with a new instruction address, do not themselves access memory. Absolute and relative forms of the jump reflect this by omitting the round brackets from their operands. Register based jump instructions such as "<code>JP (HL)</code>" include round brackets in an apparent deviation from this convention.<ref>{{Cite web |title=Z80 Relocating Macro Assembler User's Guide |url=http://z80cpu.eu/mirrors/oldcomputers.dyndns.org/manuals/z80asm.pdf |url-status=dead |archive-url=https://web.archive.org/web/20110720173724/http://z80cpu.eu/mirrors/oldcomputers.dyndns.org/manuals/z80asm.pdf |archive-date=July 20, 2011 |access-date=June 4, 2009 |page=B–2}}</ref>}} * All load and store instructions use the same mnemonic name, LD, for LOAD (a return to the simplistic Datapoint 2200 vocabulary); other common instructions, such as ADD and INC, use the same mnemonic regardless of addressing mode or operand size. This is possible because the operands themselves carry enough information. These principles made it straightforward to find names and forms for all new Z80 instructions, as well as [[Orthogonality (programming)|orthogonalizations]] of old ones, such as <code>LD BC,1234</code>. Apart from naming differences, and despite a certain discrepancy in basic register structure, the Z80 and [[Intel 8086|8086]] syntax are virtually [[isomorphic]] for a large portion of instructions. Only quite superficial similarities (such as the word MOV, or the letter X, for extended register) exist between the 8080 and 8086 assembly languages, although 8080 programs can be translated to 8086 assembly language by [[Assembly language translator|translator programs]].<ref name="Scanlon 1988" /><ref name="Nelson 1989" /> === Instruction set and encoding === The Z80 uses 252 out of the available 256 codes as single byte opcodes ("root instruction" most of which are inherited from the 8080); the four remaining codes are used extensively as [[opcode prefix]]es:<ref name="Zilog 1995">{{Cite web |year=1995 |title=Z80 CPU Introduction |url=http://www.z80.info/z80brief.htm |url-status=live |archive-url=https://web.archive.org/web/20231220144519/http://www.z80.info/z80brief.htm |archive-date=December 20, 2023 |publisher=[[Zilog]] |quote=It has a language of 252 root instructions and with the reserved 4 bytes as prefixes, accesses an additional 308 instructions.}}</ref> CB and ED enable extra instructions, and DD or FD select IX+d or IY+d respectively (in some cases without displacement d) in place of HL. This scheme gives the Z80 a large number of permutations of instructions and registers; Zilog categorizes these into 158 different "instruction types", 78 of which are the same as those of the Intel 8080<ref name="Zilog 1995" /> (allowing operation of all 8080 programs on a Z80). The Zilog documentation<ref>{{Cite web |year=1976 |title=Z80-CPU Instruction Set |url=https://usermanual.wiki/Document/ZilogZ80CPUTechnicalManual.2406416115/view#23 |url-status=live |archive-url=https://web.archive.org/web/20231105184525/https://usermanual.wiki/Document/ZilogZ80CPUTechnicalManual.2406416115/view#23 |archive-date=November 5, 2023 |access-date=July 20, 2021 |publisher=[[Zilog]] |page=19 |type=PDF}}</ref> further groups instructions into the following categories (most from the 8080, others entirely new like the block and bit instructions, and others 8080 instructions with more versatile addressing modes, like the 16-bit loads, I/O, rotates/shifts and relative jumps): * Load and exchange * Block transfer and search * Arithmetic and logical * Rotate and shift * Bit manipulation (set, reset, test) * Jump, call and return * Input/output * Basic CPU control No explicit multiply instructions are available in the original Z80,<ref>{{Cite book |last1=Sanchez |first1=Julio |title=Software Solutions for Engineers And Scientists |last2=Canton |first2=Maria P. |date=2008 |publisher=Taylor & Francis |isbn=978-1-4200-4302-0 |page=65 |quote=The 8-bit microprocessors that preceded the 80x86 family (such as the Intel 8080, the Zilog Z80, and the Motorola) did not include multiplication.}}</ref> though registers A and HL can be multiplied by powers of two with ADD A,A and ADD HL,HL instructions (similarly IX and IY also). Shift instructions can also multiply or divide by powers of two. Different sizes and variants of additions, shifts, and rotates have somewhat differing effects on flags because most of the flag-changing properties of the 8080 were copied. However, the parity flag bit P of the 8080 (bit 2) is called P/V (parity/overflow) in the Z80 as it serves the additional purpose of a twos complement overflow indicator, a feature lacking in the 8080. Arithmetic instructions on the Z80 set it to indicate overflow rather than parity, while bitwise instructions still use it as a parity flag. (This introduces a subtle incompatibility of the Z80 with code written for the 8080, as the Z80 sometimes indicates signed overflow where the 8080 would indicate parity, possibly causing the logic of some practical 8080 software to fail on the Z80.{{efn|For example, on the 8080, a programmer might test the parity of a byte by {{code|ADD}}ing zero to it, by {{code|SUB}}tracting zero from it, or by {{code|OR}}ing or {{code|XOR}}ing it with zero; all of these are single-instruction operations of the same speed and size, on both the 8080 and the Z80. If the programmer happened to choose to test parity by {{code|OR}}ing or {{code|XOR}}ing with zero, then the Z80 will execute the program correctly, but if the programmer chose to test parity by {{code|ADD}}ing or {{code|SUB}}tracting zero, then the Z80 will always reset the P/V flag to zero (since adding or subtracting zero never causes an overflow or underflow) instead of assigning P to correctly indicate the parity of the byte (as the 8080—or 8085—would), and the program may fail. Nothing in the Intel programming manuals or other documentation for the 8080 discouraged use of arithmetic instructions, or prescribed using logical instructions, to test parity, so there is no reason that an 8080 programmer exercising recommended good programming practice should be expected to have chosen one of the ways that will work on the Z80 over one of the ways that will not work.}}) This new overflow flag is used for all new Z80-specific 16-bit operations ({{code|ADC}}, {{code|SBC}}) as well as for 8-bit arithmetic operations, while the 16-bit operations inherited from the 8080 ({{code|ADD}}, {{code|INC}}, {{code|DEC}}) do not affect it. Also, bit 1 of the flags register (a spare bit on the 8080) is used as a flag N that indicates whether the last arithmetic instruction executed was a subtraction or addition. The Z80 version of the {{code|DAA}} instruction (decimal adjust accumulator for BCD arithmetic) checks the N flag and behaves accordingly, so a (hypothetical) subtraction followed later by {{code|DAA}} will yield a different result on an old 8080 than on the Z80. However, this would likely be erroneous code on the 8080, as {{code|DAA}} was defined for addition only on that processor. The Z80 has six new {{code|LD}} instructions that can load the DE, BC, and SP register pairs from memory, and load memory from these three register pairs—unlike the 8080.<ref name="Durda 2012" /> As on the 8080, load instructions do not affect the flags (except for the special-purpose I and R register loads). A result of a regular encoding (common with the 8080) is that each of the 8-bit registers can be loaded from themselves (e.g. {{code|LD A,A}}). This is effectively a {{code|NOP}}. New block transfer instructions can move up to 64 kilobytes from memory to memory or between memory and I/O peripheral ports. Block instructions {{code|LDIR}} and {{code|LDDR}} ('''l'''oa'''d''', '''i'''ncrement/'''d'''ecrement, '''r'''epeat) use HL to point to the source address, DE to the destination address, and BC as a byte counter. Bytes are copied from source to destination, the pointers are incremented or decremented, and the byte counter is decremented until BC reaches zero. Non-repeating versions {{code|LDI}} and {{code|LDD}} move a single byte and bump the pointers and byte counter, which if it becomes zero resets the P/V flag. Corresponding memory-to-I/O instructions {{code|INIR}}, {{code|INDR}}, {{code|OTIR}}, {{code|OTDR}}, {{code|INI}}, {{code|IND}}, {{code|OUTI}} and {{code|OUTD}} operate similarly, except that B, not BC, is used as the byte counter.{{sfnp|Ciarcia|1981|p=86}}<ref>{{Cite book |last=HAYES |first=JOHN P. |title=Computer Architecture and Organization |year=1978 |isbn=0-07-027363-4 |page=423}}</ref> The Z80 can input and output any register to an I/O port using register C to designate the port. (The 8080 only performs I/O through the accumulator A, using a direct port address specified in the instruction; a self-modifying code technique is required to use a variable 8080 port address.) The last group of block instructions perform a {{code|CP}} compare operation between the byte at (HL) and the accumulator A. Register pair DE is not used. The repeating versions {{code|CPIR}} and {{code|CPDR}} only terminate if BC goes to zero or a match is found. HL is left pointing to the byte after ({{code|CPIR}}) or before ({{code|CPDR}}) the matching byte. If no match is found, the Z flag is reset. There are non-repeating versions {{code|CPI}} and {{code|CPD}}. Unlike the 8080, the Z80 can jump to a relative address ({{code|JR}} instead of {{code|JP}}) using a shorter instruction with a signed 8-bit displacement. There are unconditional and conditional forms of this instruction. Only the zero and carry conditions can be tested. (All 8080 jumps and calls, conditional or not, are three-byte instructions.) If jump is taken, the two-byte {{code|JR}} instructions are slower than the 8080-style three-byte {{code|JP}} instructions; if not taken, {{code|JR}} instructions are quicker. A two-byte instruction specialized for program looping is also new to the Z80: {{code|DJNZ}} ('''d'''ecrement '''j'''ump if '''n'''on-'''z'''ero) takes a signed 8-bit displacement as an operand. The B register is decremented, and if the result is nonzero, then program execution jumps relative to PC; the flags remain unaltered. To perform an equivalent loop on an 8080 requires separate {{code|DEC}} and conditional jump (to a two-byte absolute address) instructions (totalling four bytes), and the {{code|DEC}} alters the flag register. The index register (IX/IY, often abbreviated XY) instructions can be useful for accessing data organised in fixed heterogenous structures (such as [[record (computer science)|records]]) or at fixed offsets relative a variable base address (as in [[recursive]] [[stack frame]]s) and can also reduce code size by removing the need for multiple short instructions using non-indexed registers. However, although they may save speed in some contexts when compared to long/complex "equivalent" sequences of simpler operations, they incur a lot of additional CPU time (e.g., 19 T-states to access one indexed memory location vs. as little as 11 to access the same memory using HL and {{code|INC}} to point to the next). Thus, for simple or linear accesses of data, use of IX and IY tend to be slower and occupy more memory. Still, they may be useful in cases where the "main" registers are all occupied, by removing the need to save/restore registers. Their officially undocumented 8-bit halves (see below) can be especially useful in this context, for they incur less slowdown than their 16-bit parents. Similarly, instructions for 16-bit additions are not particularly fast (11 clocks) in the original Z80 (being 1 clock slower than in the 8080/8085); nonetheless, they are about twice as fast as performing the same calculations using 8-bit operations, and equally important, they reduce register usage. It was not uncommon for programmers to "poke" different offset displacement bytes (which were typically calculated dynamically) into indexed instructions; this is an example of [[self-modifying code]], which was regular practice on nearly all early 8-bit processors with non-[[Instruction pipelining#Special situations|pipelined]] execution units. The index registers have a parallel instruction to {{code|JP (HL)}}, which is {{code|JP (XY)}}. This is often seen in stack-oriented languages like [[Forth (programming language)|Forth]], which at the end of every Forth word (atomic subroutines comprising the language) must jump unconditionally back to their thread interpreter routines. Typically this jump instruction appears hundreds of times in an application, and using {{code|JP (XY)}} rather than {{code|JP THREAD}} saves a byte and two T-states for each occurrence. This naturally makes the index register unavailable for any other use, or else the need to constantly reload it would negate its efficiency. The 10-year-newer microcoded [[Z180]] design could initially afford more "chip area", permitting a slightly more efficient implementation (using a wider [[Arithmetic logic unit|ALU]], among other things); similar things can be said for the [[Zilog Z800|Z800]], [[Z280]], and [[Z380]]. However, it was not until the fully pipelined [[Zilog eZ80|eZ80]] was launched in 2001 that those instructions finally became approximately as cycle-efficient as it is technically possible to make them, i.e. given the Z80 encodings combined with the capability to do an 8-bit read or write every clock cycle.{{Citation needed|date=July 2011}} ==== Undocumented instructions ==== The index registers, IX and IY, were intended as flexible 16-bit pointers, enhancing the ability to manipulate memory, stack frames and data structures. Officially, they were treated as 16-bit only. In reality they were implemented as a pair of 8-bit registers,<ref>{{Cite book |last=Froehlich |first=Robert A. |url=https://archive.org/details/freesoftwarecata0000froe/ |title=The free software catalog and directory |date=1984 |publisher=Crown Publishers |isbn=978-0-517-55448-7 |page=133 |quote=Undocumented Z80 codes allow 8 bit operations with IX and IY registers. |url-access=registration}}</ref> in the same fashion as the HL register, which is accessible either as 16 bits or separately as the ''H''igh and ''L''ow registers. The binary opcodes (machine language) were identical, but preceded by a new opcode prefix.<ref name="undocz80">{{Cite web |last=Bot |first=Jacco J. T. |title=Z80 Undocumented Instructions |url=http://www.z80.info/z80undoc.htm |url-status=live |archive-url=https://web.archive.org/web/20231223185034/http://z80.info/z80undoc.htm |archive-date=December 23, 2023 |website=Home of the Z80 CPU |quote=If an opcode works with the registers HL, H or L then if that opcode is preceded by #DD (or #FD) it works on IX, IXH or IXL (or IY, IYH, IYL), with some exceptions. The exceptions are instructions like LD H,IXH and LD L,IYH.}}</ref> Zilog published the opcodes and related mnemonics for the intended functions, but did not document the fact that every opcode that allowed manipulation of the H and L registers was equally valid for the 8 bit portions of the IX and IY registers. For example, the opcode 26h followed by an immediate byte value {{code|(LD H,n)}} will load that value into the H register. Preceding this two-byte instruction with the IX register's opcode prefix, DD, would instead result in the most significant 8 bits of the IX register being loaded with that same value. A notable exception to this would be instructions similar to {{code|LD H,(IX+d)}} which make use of both the HL and IX or IY registers in the same instruction;<ref name="undocz80" /> in this case the DD prefix is only applied to the (IX+d) portion of the instruction. The halves of the XY registers could also hold operands for 8-bit arithmetic, logical and compare instructions, sparing the regular 8-bit registers for other use. The undocumented ability to increment and decrement the upper half of an index register made it easy to expand the range of the normal indexed instructions, without having to resort to the documented {{code|ADD/SBC XY,DE}} or {{code|ADD/SBC XY,BC}}. There are several other undocumented instructions as well.<ref>Robin Nixon ''The Amstrad Notepad Advanced User Guide'', Robin Nixon, 1993, {{ISBN|1-85058-515-6}}, pages 219–223.</ref> Undocumented or [[illegal opcode]]s are not detected by the Z80 and have various effects, some of which are useful. However, as they are not part of the formal definition of the instruction set, different implementations of the Z80 are not guaranteed (or especially likely) to work the same way for every undocumented opcode. ==== Bugs ==== The {{code|OTDR}} instruction does not conform to the Z80 documentation. Both the {{code|OTDR}} and {{code|OTIR}} instructions are supposed to leave the carry (C) flag unmodified. The {{code|OTIR}} instruction operates correctly; however, during the execution of the {{code|OTDR}} instruction, the carry flag takes the results of a spurious compare between the accumulator (A) and the last output of the {{code|OTDR}} instruction.<ref name="Young 1998" /> === Example code === The following Z80 assembly source code is for a subroutine named <code>memcpy</code> that copies a block of data bytes of a given size from one location to another. Important: the example code does not handle the case where the destination block overlaps the source; a serious limitation, but one that is irrelevant for some applications—such as, especially, when the source is in ROM and the destination in RAM, so they can never overlap. The data block is copied one byte at a time, and the data movement and looping logic utilizes 16-bit operations. It demonstrates a variety of instructions but in practice it would not be coded this way as the Z80 has a single instruction that will replace this entire subroutine: <code>LDIR</code>. The sample code will move one byte every 46 T-states. Substituting the <code>LDIR</code> instruction will move each byte in only 21 T-states. Note that the assembled code is binary-compatible with the Intel 8080 and 8085 CPUs. {| |-valign="top" |<syntaxhighlight lang="text" highlight="16"> 1000 1000 1000 F5 1001 7E 1002 12 1003 23 1004 13 1005 0B 1006 78 1007 B1 1008 C2 01 10 100B F1 100C C9 100D </syntaxhighlight> |<syntaxhighlight lang="tasm" highlight="16"> ; memcpy -- ; Copy a block of memory from one location to another. ; This routine is the equivalent of LDIR ; ; Entry registers ; HL - Address of source data block ; DE - Address of destination data block ; BC - Number of bytes to copy ; ; Return registers ; HL - First byte after source data block ; DE - First byte after destination data block ; BC - Zero ; (LDIR does not fully save AF. H, P/V, and N are reset.) org 1000h ; Origin at 1000h memcpy public push af ; Save AF like LDIR loop ld a,(hl) ; Copy 1 source byte ld (de),a ; to its destination inc hl ; Bump source pointer inc de ; Bump dest pointer dec bc ; Count the copied byte ld a,b ; Test BC for zero or c ; If BC != 0, jp nz,loop ; repeat the loop pop af ; Restore AF ret ; Return end </syntaxhighlight> |} === Instruction execution === Each instruction is executed in steps that are usually termed [[machine cycle]]s (M-cycles), each of which can take between three and six clock periods (T-states).<ref>{{Cite book |url=https://www.zilog.com/docs/z80/um0080.pdf#G5.1130345 |title=Z80 Family CPU User Manual |publisher=[[Zilog]] |year=2016 |page=7 |chapter=Timing |id=UM008011-0816 |access-date=January 5, 2024 |archive-url=https://web.archive.org/web/20231226131929/http://www.zilog.com/docs/z80/um0080.pdf#G5.1130345 |archive-date=December 26, 2023 |url-status=live}}</ref> Each M-cycle corresponds roughly to one memory access or internal operation. Multiple instructions actually end during the M1 of the ''next'' instruction which is known as a ''fetch/execute overlap''. {| class="wikitable" |+ Examples of typical instructions (R=read, W=write) ! Total M-cycles ! T-states ! instruction ! M1 ! M2 ! M3 ! M4 ! M5 ! M6 |- | 1{{sfnp|Ciarcia|1981|p=65}} | 4<ref name="Zilog 2005" /> | <syntaxhighlight lang="nasm" inline>INC B</syntaxhighlight> | opcode | || | || || |- | 2<ref>{{Cite book |last=Zaks |first=Rodnay |url=https://archive.org/details/Programming_The_Z80_Third_Edition_Rodnay_Zaks/ |title=Programming the Z80 |date=1989 |publisher=Sybex |isbn=978-0-89588-069-7 |page=200 |quote=ADD A, n Add accumulator with immediate data n. MEMORY Timing: 2 M cycles; 7 T states. |issue=69}}</ref> | 7 | <syntaxhighlight lang="nasm" inline>ADD A,n</syntaxhighlight> | opcode | n | || | || |- | 3{{sfnp|Ciarcia|1981|p=63}} | 11 | <syntaxhighlight lang="nasm" inline>ADD HL,DE</syntaxhighlight> | opcode | internal | internal | || || |- | 4{{sfnp|Ciarcia|1981|p=77}} | 15 | <syntaxhighlight lang="nasm" inline>SET b,(HL)</syntaxhighlight> | prefix | opcode | R(HL), set | W(HL) | || |- | 5{{sfnp|Ciarcia|1981|p=36}} | 19 | <syntaxhighlight lang="nasm" inline>LD (IX+d),n</syntaxhighlight> | prefix | opcode | d | n,add | W(IX+d) || |- | 6{{sfnp|Ciarcia|1981|p=58}} | 23 | <syntaxhighlight lang="nasm" inline>INC (IY+d)</syntaxhighlight> | prefix | opcode | d | add |R(IY+d),inc | W(IY+d) |} The Z80 machine cycles are sequenced by an internal [[state machine]] which builds each M-cycle out of 3, 4, 5 or 6 T-states depending on context. This avoids cumbersome asynchronous logic and makes the control signals behave consistently at a wide range of clock frequencies. It also means that a higher frequency crystal must be used than without this subdivision of machine cycles (approximately 2–3 times higher). It does not imply tighter requirements on [[memory access time]]s, since a high resolution clock allows more precise control of memory timings and so memory can be active in parallel with the CPU to a greater extent, allowing more efficient use of available memory bandwidth.{{citation needed|date=December 2012}} One central example of this is that, for [[opcode fetch]], the Z80 combines two full clock cycles into a memory access period (the M1-signal). In the Z80 this signal lasts for a relatively larger part of the typical instruction execution time than in a design such as the [[Motorola 6800|6800]], [[MOS Technology 6502|6502]], or similar, where this period would typically last typically 30-40% of a clock cycle.{{citation needed|date=November 2012}} With memory chip affordability (i.e. access times around 450-250 ns in the 1980s{{citation needed|date=November 2012}}) typically determining the fastest possible access time, this meant that such designs were locked to a significantly longer clock cycle (i.e. lower internal clock speed) than the Z80. Memory was generally slow compared to the state machine sub-cycles (clock cycles) used in contemporary microprocessors. The shortest machine cycle that could safely be used in embedded designs has therefore often been limited by memory access times, not by the maximum CPU frequency (especially so during the home computer era). However, this relation has slowly changed during the last decades, particularly regarding [[Static random access memory|SRAM]]; cacheless, single-cycle designs such as the eZ80 have therefore become much more meaningful recently. The content of the refresh register R is sent out on the lower half of the address bus along with a refresh control signal while the CPU is decoding and executing the fetched instruction. During refresh the contents of the Interrupt register I are sent out on the upper half of the address bus.<ref>{{Cite book |url=https://www.zilog.com/docs/z80/um0080.pdf#G5.1012169 |title=Z80 Family CPU User Manual |publisher=[[Zilog]] |year=2016 |page=3 |chapter=Special-Purpose Registers |id=UM008011-0816 |access-date=January 5, 2024 |archive-url=https://web.archive.org/web/20231226131929/http://www.zilog.com/docs/z80/um0080.pdf#G5.1012169 |archive-date=December 26, 2023 |url-status=live}}</ref> === Compatible peripherals === Zilog introduced a number of peripheral parts for the Z80, which all support the Z80's interrupt handling system and I/O address space. These include the counter/timer channel (CTC),<ref>{{Cite web |last=<!--Staff writer(s); no by-line.--> |date=2001 |title=Z80 Family CPU Peripherals User Manual |url=http://datasheet.eeworld.com.cn/pdf/ZILOG/68012_Z80.pdf |url-status=dead |archive-url=https://web.archive.org/web/20140502033449/http://datasheet.eeworld.com.cn/pdf/ZILOG/68012_Z80.pdf |archive-date=May 2, 2014 |access-date=April 30, 2014 |website=EEWORLD Datasheet |publisher=ZiLOG}}</ref> the SIO (serial input/output), the DMA (direct memory access), the PIO (parallel input/output) and the DART (dual asynchronous receiver–transmitter). As the product line developed, low-power, high-speed and [[CMOS]] versions of these chips were introduced. <gallery mode="packed"> File:Basic Measuring Instruments - Math Processor 83002190 - Zilog Z80 PIO Z84C2008PEC-3919.jpg|PIO Z84C2008 File:Basic Measuring Instruments - Math Processor 83002190 - Zilog Z80 CTC Z84C3008PEC-3918.jpg|CTC Z84C3008 File:Basic Measuring Instruments - Math Processor 83002190 - Zilog Z80 SIO Z84C4008PEC-3920.jpg|SIO Z84C4008 </gallery> Like the 8080, 8085 and 8086 processors, but unlike processors such as the Motorola 6800 and MOS Technology 6502, the Z80 and 8080 has a separate control line and address space for I/O instructions. While some Z80-based computers such as the [[Osborne 1]] used "Motorola-style" [[Memory-mapped I/O|memory mapped input/output]] devices, usually the I/O space was used to address one of the Zilog peripheral chips compatible with the Z80. During the timing for an I/O read or an I/O write operation, a single wait cycle is automatically inserted by the Z80.<ref>{{Cite web |title=Sharp 1986 Semiconductor Data Book |url=http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=225 |access-date=January 1, 2024 |page=218 |archive-date=January 1, 2024 |archive-url=https://web.archive.org/web/20240101005825/http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=225 |url-status=live }}</ref> Zilog I/O chips supported the Z80's new mode 2 interrupts which simplified interrupt handling for large numbers of peripherals. The Z80 was officially described as supporting 16-bit (64 KB) memory addressing, and 8-bit (256 ports) I/O-addressing. All I/O instructions actually assert the entire 16-bit address bus. OUT (C),reg and IN reg,(C) places the contents of the entire 16-bit BC register on the address bus;<ref name="Young 1998">{{Cite web |last=Young |first=Sean |date=October 1998 |title=Z80 Undocumented Features (in software behaviour) |url=http://z80.info/z80undoc3.txt |url-status=live |archive-url=https://web.archive.org/web/20231225235537/http://z80.info/z80undoc3.txt |archive-date=December 25, 2023 |quote=The I/O instructions use the whole of the address bus, not just the lower 8 bits. So in fact, you can have 65536 I/O ports in a Z80 system (the Spectrum uses this). IN r,(C), OUT (C),r and all the I/O block instructions put the whole of BC on the address bus. IN A,(n) and OUT (n),A put A*256+n on the address bus.}}</ref> OUT (n),A and IN A,(n) places the contents of the A register on b8–b15 of the address bus and n on b0–b7 of the address bus. A designer could choose to decode the entire 16-bit address bus on I/O operations in order to take advantage of this feature, or use the high half of the address bus to select subfeatures of the I/O device. This feature has also been used to minimise decoding hardware requirements, such as in the [[Amstrad CPC]]/[[Amstrad PCW|PCW]] and [[ZX81]]. == Second sources and derivatives == === Second sources === Mostek, which produced the first Z80 for Zilog, offered it [[second-source]] as MK3880. SGS-Thomson (now [[STMicroelectronics]]) was a second source, too, with their Z8400. Sharp and [[NEC]] developed second sources for the NMOS Z80, the LH0080 and μPD780C, respectively. The LH0080 was used in various home computers and personal computers made by Sharp and other Japanese manufacturers, including [[Sony]] [[MSX]] computers, and a number of computers in the [[Sharp MZ]] series.<ref>{{Cite web |title=Overview of the SHARP MZ-series |url=http://www.sharpmz.org/mzovview.htm |url-status=dead |archive-url=https://web.archive.org/web/20080327200542/http://www.sharpmz.org/mzovview.htm |archive-date=March 27, 2008 |access-date=July 28, 2011 |website=SharpMZ.org |quote=Most MZ's use the 8bit CPU LH0080 / Z80 [...]}}</ref> Sharp developed the LH0080A and LH0080B to operate at frequencies of 4 MHz and 6 MHz, respectively.<ref>{{Cite book |url=http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=217 |title=1986 Semiconductor Data Book |publisher=[[Sharp Corporation]] |year=1986 |page=210 |chapter=LH0080/LH0080A/LH0080B |archive-url=https://web.archive.org/web/20240101124118/http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=217 |archive-date=January 1, 2024 |url-status=live |accessdate=January 1, 2024}}</ref> Sharp also developed LH0083<ref>{{Cite web |title=Sharp 1986 Semiconductor Data Book |url=http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=262 |access-date=January 13, 2024 |pages=255–269 |archive-date=January 20, 2024 |archive-url=https://web.archive.org/web/20240120013519/http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=262 |url-status=live }}</ref> compatible with Z80 DMA. Toshiba made a CMOS-version, the TMPZ84C00, which is believed{{by whom | date = December 2010}} (but not verified) to be the same design also used by Zilog for its own CMOS Z84C00. There were also Z8400, Z80-chips made by [[GoldStar]] (now [[LG]]) and the BU18400 series of Z80-clones (including DMA, PIO, CTC, DART and SIO) in [[NMOS logic|NMOS]] and [[CMOS]] made by [[ROHM Electronics]]. The LH5080,<ref>{{Cite web |title=Sharp 1986 Semiconductor Data Book |url=http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=303 |access-date=January 20, 2024 |pages=296–301 |archive-date=January 20, 2024 |archive-url=https://web.archive.org/web/20240120013519/http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=303 |url-status=live }}</ref> LH5081,<ref>{{Cite web |title=Sharp 1986 Semiconductor Data Book |url=http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=309 |access-date=January 28, 2024 |pages=302–306 |archive-date=January 28, 2024 |archive-url=https://web.archive.org/web/20240128011432/http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=309 |url-status=live }}</ref> and LH5082,<ref>{{Cite web |title=Sharp 1986 Semiconductor Data Book |url=http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=314 |access-date=January 28, 2024 |pages=307–311 |archive-date=January 28, 2024 |archive-url=https://web.archive.org/web/20240128011432/http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=314 |url-status=live }}</ref> which are CMOS versions of the Z80, PIO, and CTC respectively, are manufactured by Sharp. In [[East Germany]], an unlicensed clone of the Z80, known as the [[U880]], was manufactured. It was used extensively in [[VEB Robotron|Robotron]]'s and VEB Mikroelektronik Mühlhausen's computer systems (such as the [[KC85]]-series) and also in multiple self-made computer systems. In [[Romania]] another unlicensed clone could be found, named [[MMN80CPU]] and produced by [[Electronics industry in the Socialist Republic of Romania|Microelectronica]], used in home computers like TIM-S, HC, COBRA. Also, several clones of Z80 were created in the [[Soviet Union]], notable ones being the [[T34 (microprocessor)|T34BM1]], also called [[КР1858ВМ1]] (parallelling the Soviet 8080-clone [[KR580VM80A]]). The first marking was used in pre-production series, while the second had to be used for a larger production. Though, due to the collapse of Soviet microelectronics in the late 1980s, there are more T34BM1s than КР1858ВМ1s.{{citation needed|date=May 2013}} <gallery mode="packed"> File:KL Mostek MK3880P Z80.jpg|[[Mostek]] Z80: MK3880 File:KL NEC uPD780C.jpg|[[NEC μPD780C]] File:Sharp LH0080A.jpg|[[Sharp LH0080]] File:TMPZ84C00.jpg|Toshiba Z84C00 File:KL KME U880D-1.jpg|East Germany RFT [[U880]]D File:KL USSR T34BM1 Z80 Black Background.jpg|Soviet T34BM1 Z80 clone </gallery> === Derivatives === ; Compatible with the original Z80: * [[Hitachi]] developed the [[Hitachi HD64180|HD64180]], a microcoded and partially dynamic Z80 in CMOS, with on-chip peripherals and a simple MMU, giving a 1 [[Megabyte|MB]] address space. It was later second sourced by Zilog, initially as the Z64180, and then in the form of the slightly modified [[Zilog Z180]]<ref>{{Cite web |last=Ganssle |first=Jack G. |date=1992 |title=The Z80 Lives! |url=http://www.z80.info/z80lives.htm |quote=The 64180 is a Hitachi-supplied Z80 core with numerous on-chip "extras". Zilog's version is the Z180, which is essentially the same part. |access-date=July 17, 2009 |archive-date=May 1, 2009 |archive-url=https://web.archive.org/web/20090501035250/http://www.z80.info/z80lives.htm |url-status=live }}</ref> which has bus protocol and timings better adapted to Z80 peripheral chips. Z180 has been maintained and further developed under Zilog's name, the newest versions being based on the fully static S180/L180 core with low power draw and EMI (noise). * [[Toshiba]] developed the 84-pin Z84013 / Z84C13 and the 100 pin Z84015 / Z84C15 series of "intelligent peripheral controllers", basically ordinary NMOS and CMOS Z80 cores with Z80 peripherals, [[watchdog timer]], [[Power-on reset|power on reset]], and wait state generator on the same chip. Manufactured by [[Sharp Corporation|Sharp]] as well as Toshiba. These products are today second sourced by Zilog.<ref>{{Cite web |last=Ganssle |first=Jack G. |date=1992 |title=The Z80 Lives! |url=http://www.z80.info/z80lives.htm |quote=Both Toshiba and Zilog sell the 84013 and 84015, which are Z80 cores with conventional Z80 peripherals integrated on-board. |access-date=July 17, 2009 |archive-date=May 1, 2009 |archive-url=https://web.archive.org/web/20090501035250/http://www.z80.info/z80lives.htm |url-status=live }}</ref> * The 32-bit Z80 compatible Zilog Z380, introduced 1994, is used in telecom equipment.<ref>{{Cite web |last=Granville |first=Fran |date=August 1, 1996 |title=EDN Access — 08.01.96 Z80 turns 20 |url=https://www.edn.com/edn-access-08-01-96-z80-turns-2/ |access-date=August 7, 2023 |website=EDN |archive-date=August 7, 2023 |archive-url=https://web.archive.org/web/20230807180704/https://www.edn.com/edn-access-08-01-96-z80-turns-2/ |url-status=live }}</ref> * Zilog's fully pipelined Z80 compatible [[Zilog eZ80|eZ80]]<ref>{{Cite web |title=EZ80 ACCLAIM Product Family |url=http://www.zilog.com/index.php?option=com_product&Itemid=26&mode=showFamilyDetails&familyId=119&parent_id=77 |url-status=dead |archive-url=https://web.archive.org/web/20081220051014/http://www.zilog.com/index.php?option=com_product&Itemid=26&mode=showFamilyDetails&familyId=119&parent_id=77 |archive-date=December 20, 2008 |publisher=Zilog}}</ref> with an 8/16/24-bit word length and a linear 16 MB address space was introduced in 2001. It exists in versions with on-chip [[Static random-access memory|SRAM]] or [[Flash memory]], as well as with integrated peripherals. One variant has an on-chip [[medium access control]]ler (MAC), and available software include a [[Internet protocol suite|TCP/IP stack]]. In contrast with the Z800 and Z280, there are only a few added instructions (primarily [[Addressing mode#Important use case|load Effective Address]] (LEA), [[Addressing mode|Push Effective Address]] (PEA), and variable-address 16/24-bit loads), but instructions are instead executed between 2 and 11 times as clock cycle efficiently as on the original Z80, with a mean value around 3-5 times. It is currently specified for clock frequencies up to 50 MHz. * [[Kawasaki Heavy Industries|Kawasaki]] developed the binary compatible KL5C8400 which is approximately 1.2-1.3 times as clock cycle efficient as the original Z80 and can be clocked at up to 33 MHz. Kawasaki also produces the KL5C80A1x family, which has peripherals as well as a small RAM on chip; it is approximately as clock cycle efficient as the eZ80 and can be clocked at up to 10 MHz (2006).<ref>{{Cite book |title=Electronic Business Asia |date=1997 |publisher=Cahners Asia Limited |page=5 |quote=Kawasaki's KL5C80A12, KL5C80A16 and KL5C8400 are high speed 8-bit [[Microcontroller|MCUs]] and CPU. Their CPU code, KC80 is compatible with Zilog's Z80 at binary level. KC80 executes instructions about four times faster than Z80 at the same clock rate}}</ref> * {{anchor|uPD9002}}The NEC μPD9002 was a hybrid CPU compatible with both Z80 and [[x86]] families. * The Chinese Actions Semiconductor's audio processor family of chips (ATJ2085 and others) contains a Z80-compatible [[Microcontroller|MCUs]] together with a 24-bit dedicated DSP processor.<ref>{{Cite web |date=October 19, 2005 |title=Hardware specs |url=http://www.s1mp3.org/en/docs_hwspecs.php |url-status=dead |archive-url=https://web.archive.org/web/20051208030747/http://www.s1mp3.org/en/docs_hwspecs.php |archive-date=December 8, 2005 |website=S1mp3.org}}</ref> These chips are used in a number of MP3 and media player products. * The T80 (VHDL) and TV80 (Verilog) synthesizable soft cores are available from OpenCores.org.<ref>{{Cite web|url=https://opencores.org/projects/t80|title=Overview :: T80 cpu :: OpenCores|website=opencores.org|access-date=July 1, 2024|archive-date=April 1, 2024|archive-url=https://web.archive.org/web/20240401050916/https://opencores.org/projects/t80|url-status=live}}</ref> * The [[National Semiconductor]] NSC800 announced in 1980<ref>{{Cite journal |last=Rada |first=Col |date=March 1981 |title=NSC800 — a low-power high-performance microprocessor family |url=https://ieeexplore.ieee.org/document/5185558 |journal=Electronics and Power |publisher=[[Institution of Engineering and Technology]] |volume=27 |issue=3 |page=222 |doi=10.1049/ep.1981.0107 |access-date=June 1, 2021 |archive-date=October 16, 2021 |archive-url=https://web.archive.org/web/20211016131613/https://ieeexplore.ieee.org/document/5185558 |url-status=live |url-access=subscription }}</ref> is used in multiple TeleSecurity Timmann (TST) electronic cipher machines<ref>{{Cite web |date=February 27, 2018 |title=TST-4043: Data encryptor with HF-modem and FEC |url=https://www.cryptomuseum.com/crypto/tst/4043/ |url-status=live |archive-url=https://web.archive.org/web/20231105135939/https://www.cryptomuseum.com/crypto/tst/4043/ |archive-date=November 5, 2023 |website=Crypto Museum}}</ref> and the [[Canon X-07]]. The NSC800 is fully compatible with the Z-80 instruction set.<ref>{{Cite web |date=June 1992 |title=NSC800 High-Performance Low-Power CMOS Microprocessor |url=https://www.cryptomuseum.com/spy/fs5000/files/NSC800.pdf |url-status=live |archive-url=https://web.archive.org/web/20231119111122/https://www.cryptomuseum.com/spy/fs5000/files/NSC800.pdf |archive-date=November 19, 2023 |publisher=[[National Semiconductor]]}}</ref> The NSC800 uses a multiplexed bus like the 8085 but has a different pinout than the Z80.<ref>{{Cite web |date=February 15, 2015 |title=MCS-85, Zilog Z80 and National NSC800 Expansion Boards |url=https://www.cpushack.com/mcs-85-and-zilog-z80-expansion-boards/ |url-status=live |archive-url=https://web.archive.org/web/20230930171153/https://www.cpushack.com/mcs-85-and-zilog-z80-expansion-boards/ |archive-date=September 30, 2023 |website=CPU Shack}}</ref> ; Non-compatible: * The [[Toshiba TLCS]] 900 series of high volume, mostly [[Programmable ROM#OTPM|one-time programmable]] microcontrollers are based on the Z80. They share the same basic BC,DE,HL,IX,IY register structure, and largely the same instructions, but are not binary compatible, while the previous TLCS 90 is Z80-compatible.<ref>{{Cite web |title=Section 6 MOS MPU, MCU, and Peripherals Market Trends |url=http://smithsonianchips.si.edu/ice/cd/STATUS97/SEC06.PDF |url-status=dead |archive-url=https://web.archive.org/web/20110614063346/http://smithsonianchips.si.edu/ice/cd/STATUS97/SEC06.PDF |archive-date=June 14, 2011 |publisher=Integrated Circuit Engineering Corporation |page=16}}</ref> * The NEC [[78K]] series microcontrollers are based on the Z80. They share the same basic BC,DE,HL register structure, and has similar, but differently named instructions; not binary compatible. ; Partly compatible: * [[Rabbit Semiconductor]]'s [[Rabbit 2000]]/3000/4000 microprocessors/microcontrollers<ref>{{Cite book |last=Axelson |first=Jan |url=https://archive.org/details/embeddedethernet0000axel |title=Embedded Ethernet and Internet Complete |publisher=Lakeview research |year=2003 |isbn=978-1-931448-00-0 |page=93 |quote=Rabbit Semiconductor's Rabbit 3000 microprocessor, which is a much improved and enhanced derivative of ZiLOG, Inc.'s venerable Z80 microprocessor.}}</ref> are based on the [[Hitachi HD64180|HD64180]]/[[Zilog Z180|Z180]] architecture, although they are not fully binary compatible.<ref>{{Cite book |last1=Hyder |first1=Kamal |url=https://archive.org/details/embeddedsystemsd0000hyde/page/32/mode/2up |title=Embedded systems design using the Rabbit 3000 microprocessor |last2=Perrin |first2=Bob |publisher=Newnes |year=2004 |isbn=978-0-7506-7872-8 |page=32 |quote=The Rabbit parts are based closely on the Zilog Z180 architecture, although they are not binary compatible with the Zilog parts.}}</ref> ; No longer produced: * The [[ASCII Corporation]] [[R800]] was a fast 16-bit processor used in [[MSX#Evolution|MSX TurboR]] computers; it was software-, but not hardware-compatible with the Z80 (signal timing, pinout and function of pins differ from the Z80). * Zilog's NMOS [[Zilog Z800|Z800]] and CMOS [[Zilog Z280|Z280]] were 16-bit Z80 implementations (before the HD64180/Z180) with a 16 MB-paged MMU address space; they added multiple orthogonalizations and addressing modes to the Z80 instruction set. Minicomputer features — such as user and system modes, multiprocessor support, on chip MMU, on chip instruction and data cache, and so on — were seen rather as more complexity than as functionality and support for the (usually electronics-oriented) embedded systems designer; it also made it hard to predict instruction execution times.{{Citation needed|date=July 2011}} * Certain [[arcade game]]s, such as [[Buster Bros.|Pang]]/[[Buster Bros.]], use an encrypted "Kabuki" Z80 CPU manufactured by [[VLSI Technology]], where the decryption keys are stored in its internal [[NvSRAM#BBSRAM|battery-backed memory]], to avoid piracy and illegal bootleg games.<ref>{{Cite web |last=Cruz |first=Eduardo |date=November 23, 2014 |title=Capcom Kabuki CPU – Intro |url=https://arcadehacker.blogspot.com/2014/11/capcom-kabuki-cpu-intro.html |url-status=live |archive-url=https://web.archive.org/web/20231105135939/http://arcadehacker.blogspot.com/2014/11/capcom-kabuki-cpu-intro.html |archive-date=November 5, 2023 |website=Arcade Hacker}}</ref> <gallery mode="packed"> File:R800 02.jpg|ASCII [[R800]] File:HD64180 DIP.jpg|[[Hitachi HD64180]] File:Z180 PLCC 1988.png|[[Zilog Z180]] File:Z280 PLCC 1987.png|[[Zilog Z280]] File:TMPZ84C015AF 01.png|Toshiba TMPZ84C015 </gallery> == Notable uses == === Desktop computers === {{See also|list of home computers }} [[File:ColecoVision-Open-FL.jpg|thumb|right|The Z80A was used as the CPU in a number of gaming consoles, such as this [[ColecoVision]].]] During the late 1970s and early 1980s, the Z80 was used in a great number of fairly anonymous business-oriented machines with the [[CP/M]] operating system, a combination that dominated the market at the time.<ref>{{Cite book |last=Holtz |first=Herman |url=https://archive.org/details/computerworkstat0000holt |title=Computer work stations |date=1985 |publisher=Chapman and Hall |isbn=978-0-412-00491-9 |page=223 |quote=and CP/M continued to dominate the 8-bit world of microcomputers. |url-access=registration}}</ref><ref>{{Cite magazine |last=Dvorak |first=John C. |date=May 10, 1982 |title=After CP/M, object oriented operating systems may lead the field |url=https://books.google.com/books?id=bDAEAAAAMBAJ&pg=PA20 |url-status=live |archive-url=https://web.archive.org/web/20240106211122/https://books.google.com/books?id=bDAEAAAAMBAJ&pg=PA20 |archive-date=January 6, 2024 |magazine=[[InfoWorld]] |publisher=InfoWorld Media Group |page=20 |volume=4 |issue=18 |issn=0199-6649 |quote=The idea of a generic operating system is still in its infancy. In many ways it begins with CP/M and the mishmash of early 8080 and Z80 computers.}}</ref> Four well-known examples of Z80 business computers running CP/M are the [[Heathkit H89]], the portable [[Osborne 1]], the [[Kaypro]] series, and the [[Epson QX-10]]. Less well-known was the expensive high-end [[Otrona]] Attache.<ref>{{Cite web |last=Stengel |first=Steven |title=Otrona Attache |url=http://oldcomputers.net/attache.html |url-status=live |archive-url=https://web.archive.org/web/20231227190448/https://oldcomputers.net/attache.html |archive-date=December 27, 2023 |access-date=March 5, 2019 |website=Steve's Old Computer Museum}}</ref> Some systems used multi-tasking operating system software (like [[MP/M]] or [[Morrow Designs|Morrow]]'s Micronix) to share the one processor between several [[concurrent user]]s. [[File:ZX Spectrum.jpg|thumb|A [[Sinclair Research|Sinclair]] [[ZX Spectrum]] which uses a Z80 clocked at 3.5 MHz]] Multiple home computers were introduced that used the Z80 as the main processor or as a plug-in option to allow access to software written for the Z80. Notable are the [[TRS-80]] series, including the original model (later retronymed "Model I"), [[TRS-80 Model II|Model II]], [[TRS-80 Model III|Model III]], and [[TRS-80 Model 4|Model 4]], which were equipped with a Z80 as their main processor, and some (but not all) other TRS-80 models which used the Z80 as either the main or a secondary processor. Other notable machines were the [[Digital Equipment Corporation|DEC]] [[Rainbow 100]], and the [[Seequa Chameleon]], both of which featured both an [[Intel 8088]] and a Z80 CPU, to support either 8-bit CP/M-80 applications running on the Z80, or a custom MS-DOS that was not fully compatible with [[PC DOS]] applications running on the 8088. In 1981, Multitech (later to become [[Acer Inc.|Acer]]) introduced the [[Microprofessor I]], a simple and inexpensive training system for the Z80 microprocessor. Currently, it is still manufactured and sold by Flite Electronics International Limited in [[Southampton, England]]. In 1984 Toshiba introduced the Toshiba MSX HX-10 in Japan and Australia. In 1985, [[Sharp Corporation|Sharp]] introduced the [[Hotbit]] and [[Gradiente]] introduced the [[Gradiente Expert|Expert]], which became the dominant 8-bit home computers in [[Brazil]] until the late 1980s. === Portable and handheld computers === Use of the Z80 in lighter, battery-operated devices became more widespread with the availability of CMOS versions of the processor. It also inspired the development of other CMOS based processors, such as the LH5801<ref>{{Cite web |title=Sharp PC-1500 Technical Reference Manual |url=https://www.pc-1500.info/Data/Service_Manuals/PC-1500_Technical_Reference_Manual.pdf |url-status=live |archive-url=https://web.archive.org/web/20231105135940/http://www.pc-1500.info/Data/Service_Manuals/PC-1500_Technical_Reference_Manual.pdf |archive-date=November 5, 2023}}</ref> from Sharp. The [[Sharp PC-1500]], a [[BASIC]]-programmable [[pocket computer]] was released in 1981, followed by the improved [[Sharp PC-1600]] in 1986 and the [[Sharp PC-E220]] in 1991. Later models of the [[Sharp Wizard]] series of personal organizers also were Z80 based. [[Laptop]]s which could run the CP/M operating system just like the desktop machines followed with [[Epson PX-8 Geneva]] in 1984, and in 1985 the [[Epson PX-4]] and [[Bondwell-2]]. While the laptop market in subsequent years moved to more powerful [[Intel 8086]] processors and the MS-DOS operating system, light-weight Z80-based systems with a longer battery life were still being introduced, such as the [[Cambridge Z88]] in 1988 and the [[Amstrad NC100]] in 1992. The Z80-derived [[Zilog Z180|Z8S180]] also found its way into an early [[pen computing|pen-operated]] [[personal digital assistant]], the [[PenPad#PDA600|Amstrad PenPad PDA600]] in 1993. Hong Kong-based [[VTech]] produced a line of small laptop computers called 'Lasers' based on a Z80.<ref>{{Cite web |date=April 1991 |title=Poor Man's Laptop |url=https://books.google.com/books?id=0eQDAAAAMBAJ&q=laser+pc4&pg=PA120 |access-date=April 11, 2018 |website=Google Books |publisher=Popular Mechanics, April 1991, page 120}}</ref><ref>{{Cite web |title=Laser PC4 |url=https://www.oldcomputermuseum.com/laser_pc4.html |url-status=live |archive-url=https://web.archive.org/web/20231105135941/http://www.oldcomputermuseum.com/laser_pc4.html |archive-date=November 5, 2023 |access-date=April 11, 2018 |website=Old Computer Museum}}</ref> The last two were the Laser PC5<ref>{{Cite web |title=Laser PC5 from VTech |url=https://www.larwe.com/museum/laserpc5.html |url-status=live |archive-url=https://web.archive.org/web/20231105135939/http://www.larwe.com/museum/laserpc5.html |archive-date=November 5, 2023 |access-date=April 11, 2018 |website=larwe.com}}</ref> and PC6.<ref>{{Cite web |title=Laser PC6 |url=http://www.perfectsolutions.com/pc6f.asp |url-status=dead |archive-url=https://web.archive.org/web/20180521024606/http://www.perfectsolutions.com/pc6f.asp |archive-date=May 21, 2018 |access-date=April 11, 2018 |website=Perfect Solutions dot com |publisher=Perfect Solutions}}</ref> The [[Cidco MailStation]] Mivo 100, first released in 1999, was a stand-alone portable email device, with a Z80-based microcontroller.<ref>{{Cite web |title=Mailstation Development |url=http://www.fybertech.net/mailstation/info.php |url-status=live |archive-url=https://web.archive.org/web/20240106190541/http://www.fybertech.net/mailstation/info.php |archive-date=January 6, 2024 |access-date=April 18, 2021 |website=Fybertech.net}}</ref> Texas Instruments produced a line of pocket organizers (ending in 2000) using Toshiba processors built around a Z80 core; the first of these was the TI PS-6200<ref>{{Cite web |last=Woerner |first=Joerg |title=Texas Instruments PS-6200 |url=http://www.datamath.org/Personal/PS-6200.htm |url-status=live |archive-url=https://web.archive.org/web/20231105135940/http://www.datamath.org/Personal/PS-6200.htm |archive-date=November 5, 2023 |access-date=June 18, 2019 |website=Datamath Calculator Museum}}</ref> and after a lengthy production run of some dozen models culminated in their PocketMate series.<ref>{{Cite web |last=Woerner |first=Joerg |title=Texas Instruments PocketMate 100 |url=http://www.datamath.org/Personal/PM100.htm |url-status=live |archive-url=https://web.archive.org/web/20231105135939/http://www.datamath.org/Personal/PM100.htm |archive-date=November 5, 2023 |access-date=June 18, 2019 |website=Datamath Calculator Museum}}</ref> === Embedded systems and consumer electronics === [[File:PABX.jpg|thumb|Z80-based [[PABX]]. The Z80 is to the right of the chip with the hand-written white label on it.]] The Zilog Z80 has long been a popular microprocessor in [[embedded system]]s and [[microcontroller]] cores,<ref name="Heath 2003" /> where it remains in widespread use today.<ref name="Balch 2003">{{Cite book |last=Balch |first=Mark |title=Complete Digital Design: A Comprehensive Guide to Digital Electronics and Computer System Architecture |date=June 18, 2003 |publisher=[[McGraw-Hill Professional]] |isbn=0-07-140927-0 |series=Professional Engineering |location=[[New York City|New York, New York]] |page=122 |chapter=Digital Fundamentals}}</ref><ref>{{Cite book |last=Ian R. Sinclair |url=https://archive.org/details/practicalelectro0000sinc_u9l7/page/204/mode/2up |title=Practical electronics handbook |publisher=Newnes |year=2000 |isbn=978-0-7506-4585-0 |edition=5 |location=Oxford, Angleterre |page=204 |lccn=00502236 |oclc=42701044}}</ref> Applications of the Z80 include uses in [[consumer electronic]]s, industrial products, and electronic musical instruments. For example, Z80 was used in the groundbreaking music synthesizer [[Prophet-5]],<ref>{{Cite web |year=1999 |title=Gordon Reid's Vintage Synths – the Sequential Circuits Prophet 5 and Prophet 10 |url=https://www.gordonreid.co.uk/vintage/prophet.shtml |url-status=live |archive-url=https://web.archive.org/web/20231105135941/https://www.gordonreid.co.uk/vintage/prophet.shtml |archive-date=November 5, 2023 |website=gordonreid.co.uk}}</ref> as well as in the first [[MIDI]]-equipped synthesizer, the [[Prophet 600]].<ref>{{Cite web |last=Fabio |first=Adam |date=March 19, 2014 |title=Prophet 600: A Classic Synthesizer Gets Processor Upgrade |url=https://hackaday.com/2014/03/18/prophet-600-a-classic-synthesizer-gets-processor-upgrade/ |url-status=live |archive-url=https://web.archive.org/web/20231105135947/https://hackaday.com/2014/03/18/prophet-600-a-classic-synthesizer-gets-processor-upgrade/ |archive-date=November 5, 2023}}</ref> The Z80 was the basis for all [[E-mu Systems]] instruments from 1976 to 1986.<ref name="SOSSep2002">{{cite web|last=Keeble|first=Rob|title=30 Years of Emu|url=https://www.soundonsound.com/music-business/30-years-emu|website=Sound On Sound|publisher=SOS Publications Group|date=September 2002|access-date=10 January 2025}}</ref> [[Casio]] used the Z80A in its [[PV-1000]] video game console. Many early-1980s arcade video games, including the arcade game [[Pac-Man]], contain Z80 CPUs. The Z80 was used in Sega's [[Master System]] and [[Game Gear]] consoles. The [[Sega Genesis]] contains a Z80, with its own 8 KB of RAM, which runs in parallel with the MC68000 main CPU, has direct access to the system's sound chips and I/O (controller) ports, and has a switched data path to the main memory bus of the 68000 (providing access to the 64 KB main RAM, the software cartridge, and the whole video chip); in addition to providing backward compatibility with Master System games, the Z80 is often used to control and play back audio in Genesis software.{{efn|This common, but merely optional and not limiting, usage leads to the frequent but incorrect description of the Z80 in the Genesis as a "sound processor".}} Z80 CPUs were also used in the popular [[Comparison of Texas Instruments graphing calculators|TI-8x series of graphing calculators]] from [[Texas Instruments]], beginning in 1990 with the [[TI-81]], which features a Z80 clocked at 2 MHz. Most higher-line calculators in the series, starting with the [[TI-82]] and [[TI-85]], clock their Z80 CPUs at 6 MHz or higher. (A few models with TI-8x names use other CPUs, such as the M68000, but the vast majority are Z80-based. On those, it is possible to run assembled or compiled user programs in the form of Z80 machine-language code.) The [[TI-84 Plus series]], introduced in 2004, is still in production as of 2023. The [[TI-84 Plus series#TI-84 Plus CE and TI-84 Plus CE-T|TI-84 Plus CE series]], introduced in 2015, uses the Z80-derived [[Zilog eZ80]] processor and is also still in production as of 2024. In the late 1980s, a series of [[Soviet]] landline phones called "AON" featured the Z80; these phones expanded the feature set of the landline with [[caller ID]], different [[ringtone]]s based on the caller, [[speed dial]] and so forth.<ref>{{Cite web |date=January 29, 2020 |title=Making a demo for an old phone — AONDEMO |url=https://habr.com/en/post/486010/ |url-status=live |archive-url=https://web.archive.org/web/20231105140002/https://habr.com/ru/articles/486010/ |archive-date=November 5, 2023 |website=habr.com}}</ref> In the second half of the 1990s however, manufacturers of these phones switched to 8051 compatible MCUs to reduce power consumption, and prevent compact wall power adapters from overheating. == Discontinuation == On April 15, 2024, Zilog announced the discontinuation of the Z80 processor, with orders being accepted until June 14, 2024. The announcement included 13 variants of the Z80 processor, some of which were [[Dual in-line package|DIP40]] variants of the chip. Zilog will continue to manufacture the upgraded [[Zilog eZ80|eZ80]] version of the processor.<ref name="discontinuation" /> == See also == * [[S-100 bus]] * [[SymbOS]] * [[Z88DK]] * [[Micro-Professor MPF-I]], Z80 training system == Footnotes == {{Notelist}} == References == {{Reflist|refs= <ref name="Seybold 1983">{{Cite book |title=The Seybold report on professional computing |date=1983 |publisher=Seybold Publications |quote=In the 8-bit world, the two most popular microcomputers are the Z80 and 6502 computer chips.}}</ref> <ref name="Scanlon 1988">{{Cite book |last=Scanlon |first=Leo J. |url=https://archive.org/details/8086808880286ass0000scan/page/12 |title=8086/8088/80286 assembly language |date=1988 |publisher=[[Brady Books]] |isbn=978-0-13-246919-7 |page=[https://archive.org/details/8086808880286ass0000scan/page/12 12] |quote=[...] The [[8086]] is software-compatible with the [[8080]] at the assembly-language level. [...]}}</ref> <ref name="Nelson 1989">{{Cite book |last=Nelson |first=Ross P. |title=The 80386 Book: Assembly Language Programmer's Guide for the 80386 |date=January 1989 |publisher=[[Microsoft Press]] |isbn=978-1-55615-138-5 |edition=1 |series=Microsoft Programming Series |page=2 |quote=[...] An [[Intel]] translator program could convert [[8080]] assembler programs into [[8086]] assembler programs [...] |orig-year=1988}}</ref> <ref name="Zilog 2005">{{Cite book |last=Zilog |url=http://www.zilog.com/docs/z80/um0080.pdf |title=Z80 Family CPU User Manual |date=2005 |publisher=Zilog |page=5 |access-date=July 18, 2009 |archive-date=June 19, 2009 |archive-url=https://web.archive.org/web/20090619161842/http://www.zilog.com/docs/z80/um0080.pdf |url-status=live }}</ref> }} '''Sources''' * {{Cite book |last=Anderson |first=A. John |title=Foundations of computer technology |date=1994 |publisher=Chapman & Hall |isbn=0-412-59810-8 |edition=1st |location=London}} * {{Cite book |last=Ciarcia |first=Steve |author-link=Steve Ciarcia |url=https://archive.org/details/BuildYourOwnZ80ComputerSteveCiarcia |title=Build Your Own Z80 Computer – Design Guidelines and Application Notes |publisher=Byte Books |year=1981 |isbn=978-0-07-010962-9 |edition=1st}} * {{Cite interview |last=Faggin |first=Federico |title=Oral History Panel on the Development and Promotion of the Zilog Z8000 Microprocessor |last2=Peuto |first2=Bernard |last3=Shima |first3=Masatoshi |last4=Ungermann |first4=Ralph |url=https://archive.computerhistory.org/resources/access/text/2015/06/102658075-05-01-acc.pdf |date=April 27, 2007 |ref={{harvid|Faggin|Shima|Ungermann|2007}}}} == Further reading == ;Datasheets and manuals * [https://archive.org/details/19780101DatasheetZ80 ''Z80 Datasheet (NMOS)'']; Zilog; 10 pages; 1978. * [https://web.archive.org/web/20150403123548/http://bitsavers.informatik.uni-stuttgart.de/pdf/zilog/z80/Z80_DataBook.pdf ''Z80 Data Book (NMOS)'']; Zilog; 131 pages; 1978. * [http://www.zilog.com/docs/z80/ps0178.pdf ''Z80 Datasheet (NMOS and CMOS)'']; Zilog; 36 pages; 2002. [http://www.zilog.com/docs/z80/UP0102.pdf ''Errata''] * [http://www.zilog.com/docs/z80/UM0080.pdf ''Z80 User Manual (NMOS and CMOS)'']; Zilog; 332 pages; 2016. * [http://www.zilog.com/docs/z80/um0081.pdf ''Z80 Peripheral User Manual (NMOS and CMOS)'']; Zilog; 330 pages; 2001. ;Hardware books * ''[[Build Your Own Z80 Computer]] – Design Guidelines and Application Notes''; 1st Ed; [[Steve Ciarcia]]; Byte Books; 332 pages; 1981; {{ISBN|978-0070109629}}. <small>[https://archive.org/details/BuildYourOwnZ80ComputerSteveCiarcia (archive)]</small> * ''Z80 Microprocessor – Architecture, Interfacing, Programming, and Design''; 1st Ed; Ramesh Gaonkar; Macmillan; 674 pages; 1988; {{ISBN|978-0675205405}}. <small>[https://archive.org/details/Z80_Microprocessor_1988_Macmillan_Publishing/ (archive)]</small> * ''Z80 Users Manual – Pin Definitions, Control Signals, Peripherals, and More''; 1st Ed; Joseph Carr; Reston; 338 pages; 1980; {{ISBN|978-0835995177}}. <small>[https://archive.org/details/Z80_Users_Manual_1980_Reston_Publishing/ (archive)]</small> * ''Microprocessor Interfacing Techniques''; 3rd Ed; Rodnay Zaks and Austin Lesea; Sybex; 466 pages; 1979; {{ISBN|978-0-89588-029-1}}. <small>[https://archive.org/details/MicroprocessorInterfacingTechniques_3rd_ed/ (archive)]</small> ;Software books * ''Programming the Z80''; 3rd Ed; Rodnay Zaks; Sybex; 630 pages; 1980; {{ISBN|978-0895880949}}. <small>[https://archive.org/details/How_to_Program_the_Z80/ (archive)]</small> * ''Z80 Assembly Language Programming''; 1st Ed; Lance Leventhal; Osborne/McGraw-Hill; 642 pages; 1979; {{ISBN|978-0931988219}}. <small>[https://archive.org/details/Z-80_Assembly_Language_Programming_1979_Leventhal/ (archive)]</small> * ''8080/Z80 Assembly Language – Techniques for Improved Programming''; 1st Ed; Alan Miller; John Wiley & Sons; 332 pages; 1981; {{ISBN|978-0471081241}}. <small>[https://archive.org/details/8080_and_Z-80_Assembly_Language_Techniques_1981_John_Wiley_and_Sons/ (archive)]</small> * ''Z80 and 8080 Assembly Language Programming''; 1st Ed; Kathe Spracklen; Hayden; 180 pages; 1979; {{ISBN|978-0810451674}}. <small>[https://archive.org/details/z808080assemblyl00kath/ (archive)]</small> * ''Practical Microcomputer Programming – The Z80 – including Source for Resident Assembler and Debug Monitor''; 1st Ed; Walter Weller; Northern Technology; 501 pages; 1978; {{ISBN|978-0930594053}}. <small>[https://archive.org/details/Zilog-PracticalMicrocomputerProgrammingTheZ80-WJWellerOCR/ (archive)]</small> * ''Z80 Assembly Language Subroutines''; 1st Ed; Lance Leventhal and Winthrop Saville; Osborne/McGraw-Hill; 512 pages; 1983; {{ISBN|978-0931988912}}. <small>[https://archive.org/details/bitsavers_osborneboogeSubroutines1983_24203802/ (archive)]</small> * ''Undocumented Z80 Documented''; Sean Young; v0.91; 52 pages; 2005. <small>[http://www.myquest.nl/z80undocumented/ (archive)]</small> ;Reference cards * ''Reference Card for the Z80 Microprocessor''; Shirley & Nanos; Nanos Systems; 16 pages; 1981. <small>[https://archive.org/details/Z80_Microprocessor_Reference_Card/ (archive)]</small> * ''Z80 Microprocessor Instant Reference Card''; James Lewis; Micro Logic; 2 pages; 1981. <small>[https://archive.org/download/World_of_Spectrum_June_2017_Mirror/World%20of%20Spectrum%20June%202017%20Mirror.zip/World%20of%20Spectrum%20June%202017%20Mirror/sinclair/books/z/Z80CPUMicroprocessorInstantReferenceCard.pdf (archive)]</small> == External links == {{Wikibooks|Z80 Assembly}} {{Commons category|Zilog Z80}} * [http://www.z80.info/ Z80 unofficial support page] * [https://github.com/redcode/Z80/wiki/Technical-literature Z80 technical literature] * [https://github.com/redcode/Z80/wiki/Tests Z80 test collection] * [https://cheatsheets.one/tech/z80 Z80 Cheat Sheet] * [http://www.cpu-world.com/CPUs/Z80/ List of Z80 compatible chips] {{refbegin}} *{{Cite web |last=Shirriff |first=Ken |date=September 2013 |title=Reverse-engineering the Z-80: the silicon for two interesting gates explained |url=http://www.righto.com/2013/09/understanding-z-80-processor-one-gate.html |access-date=November 26, 2023 |archive-date=November 28, 2023 |archive-url=https://web.archive.org/web/20231128222913/https://www.righto.com/2013/09/understanding-z-80-processor-one-gate.html |url-status=live }} *{{Cite web |last=Shirriff |first=Ken |author-mask=1 |date=September 2013 |title=The Z-80 has a 4-bit ALU. Here's how it works |url=http://www.righto.com/2013/09/the-z-80-has-4-bit-alu-heres-how-it.html |access-date=November 16, 2021 |archive-date=September 9, 2013 |archive-url=https://web.archive.org/web/20130909224112/http://www.righto.com/2013/09/the-z-80-has-4-bit-alu-heres-how-it.html |url-status=live }} *{{Cite web |last=Shirriff |first=Ken |author-mask=1 |date=October 2014 |title=Down to the silicon: how the Z80's registers are implemented |url=http://www.righto.com/2014/10/how-z80s-registers-are-implemented-down.html |access-date=October 5, 2014 |archive-date=October 6, 2014 |archive-url=https://web.archive.org/web/20141006003133/http://www.righto.com/2014/10/how-z80s-registers-are-implemented-down.html |url-status=live }} *{{Cite web |last=Shirriff |first=Ken |author-mask=1 |date=November 2013 |title=The Z-80's 16-bit increment/decrement circuit reverse engineered |url=http://www.righto.com/2013/11/the-z-80s-16-bit-incrementdecrement.html |access-date=November 26, 2023 |archive-date=January 15, 2024 |archive-url=https://web.archive.org/web/20240115011134/http://www.righto.com/2013/11/the-z-80s-16-bit-incrementdecrement.html |url-status=live }} {{refend}} Simulators / Emulators: * [http://www.zophar.net/z80.html Z80 software emulators] * [http://www.mathematik.uni-ulm.de/users/ag/yaze-ag/ Yet Another Z80 Emulator] * [http://sourceforge.net/projects/zilogz80/ Z80 Bus Emulator for education purpose] * [https://floooh.github.io/visualz80remix/ Visual Z80 Remix] * [https://github.com/redcode/Z80 Z80 emulation library written in ANSI C] ;Boards * [http://searle.x10host.com/z80/SimpleZ80.html Grant's 7-chip Z80 computer] * [http://searle.x10host.com/cpm/index.html Grant's 9-chip Z80 computer, supports CP/M 2.2 or BASIC] * [https://github.com/linker3000/Z80-Board link3000 6-chip Z80 computer, supports CP/M 2.2] {{Zilog}} {{8bitMCUs}} {{Authority control}} [[Category:Computer-related introductions in 1976]] [[Category:Zilog microprocessors]] [[Category:Z80| ]] [[Category:Sharp Corporation products|LH-0080]] [[Category:8-bit microprocessors]]
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