Editing Zilog eZ80

{{Short description|8-bit microprocessor}}
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{{no footnotes|date=July 2009}}
{{Primary sources|date=March 2020}}
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{{Use mdy dates|date=May 2024}}
{{Infobox CPU
| name                      = Zilog eZ80
| image                     = EZ80 Microprocessor.jpg
| alt                       = A square black eZ80 microprocessor sits on a green printed circuit board with other electronic components 
| caption                   = eZ80 in a [[TI-84 Plus CE]] with 256&nbsp;KB on-chip RAM
<!------------------  General Info  ------------------->
| launching                 = <!-- Use if a CPU microarchitecture/series has not yet launched but its official release date is known -->
| produced-start            = 2001<ref>{{Cite news |last=Proven |first=Liam |date=April 26, 2024 |title=The eight-bit Z80 is dead. Long live the 16-bit Z80! |url=https://www.theregister.com/2024/04/26/long_live_16_bit_z80/ |access-date=May 29, 2024 |work=The Register |language=en}}</ref>
| produced-end              = <!-- When production ended / Discontinued date -->
| soldby                    = [[Zilog]]
| designfirm                = Zilog
| manuf1                    = Zilog
| cpuid                     = <!-- CPUID or PVR value -->
| code                      = <!-- numerical identifier for the CPU (product code) -->
<!------------------  Performance  ------------------->
| slowest                   = <!-- Lowest maximum CPU clock -->
| fastest                   = <!-- Highest maximum CPU clock -->
| slow-unit                 = <!-- Unit for slow speed. Default: GHz -->
| fast-unit                 = <!-- Unit for fast speed. Default: GHz -->
| fsb-slowest               = <!-- Slowest FSB speed -->
| fsb-fastest               = <!-- Fastest FSB speed -->
| fsb-slow-unit             = <!-- Unit for slow speed. Default: MHz -->
| fsb-fast-unit             = <!-- Unit for fast speed. Default: MHz -->
| hypertransport-slowest    = <!-- Slowest HyperTransport speed -->
| hypertransport-fastest    = <!-- Fastest HyperTransport speed -->
| hypertransport-slow-unit  = <!-- Unit for slow speed. Default: GT/s -->
| hypertransport-fast-unit  = <!-- Unit for fast speed. Default: GT/s -->
| qpi-slowest               = <!-- Slowest QPI (QuickPath Interconnect) speed -->
| qpi-fastest               = <!-- Fastest QPI speed -->
| qpi-slow-unit             = <!-- Unit for slow speed. Default: GT/s -->
| qpi-fast-unit             = <!-- Unit for fast speed. Default: GT/s -->
| dmi-slowest               = <!-- Slowest DMI (Direct Media Interface) speed -->
| dmi-fastest               = <!-- Fastest DMI speed -->
| dmi-slow-unit             = <!-- Unit for slow speed. Default: GT/s -->
| dmi-fast-unit             = <!-- Unit for fast speed. Default: GT/s -->
| data-width                = <!-- Data bus width in bits -->
| address-width             = <!-- Address bus width in bits -->
| virtual-width             = <!-- Virtual address bus width in bits -->
<!------------------  Cache  ------------------->
| l1cache                   = <!-- Level 1 cache size -->
| l2cache                   = <!-- Level 2 cache size -->
| l3cache                   = <!-- Level 3 cache size -->
| l4cache                   = <!-- Level 4 cache size -->
| llcache                   = <!-- Last Level cache size -->
<!------------------  Architecture and classification  ------------------->
| application               = <!-- Typical application (Embedded, Mobile, Desktop, Server) -->
| size-from                 = <!-- First fabrication size -->
| size-to                   = <!-- Second fabrication size -->
| microarch                 = <!-- Microarchitecture of the CPU -->
| arch                      = Z80{{efn|Backwards compatible with Intel 8080}}
| instructions              = <!-- Instruction sets -->
| extensions                = <!-- Extensions to the instructions -->
| numinstructions           = <!-- Number of instructions -->
<!------------------  Physical specifications  ------------------->
| transistors               = <!-- Number of transistors, transistor count -->
| numcores                  = <!-- Number of cores (2 for dual-core) -->
| amountmemory              = <!-- Amount of system RAM for SoC or SiP -->
| gpu                       = <!-- Integrated GPU -->
| co-processor              = <!-- A [[co-processor]](s) used together -->
| pack1                     = <!-- (1..5) Names of CPU packages -->
| sock1                     = <!-- (1..9) Names of the sockets that the CPU was made for -->
<!------------------  Products, models, variants  ------------------->
| core1                     = <!-- (1..9) Names of the cores -->
| pcode1                    = <!-- (1..9) Product code names -->
| model1                    = <!-- (1..9) Model names -->
| brand1                    = <!-- (1..9) Marketing names of the CPU -->
| variant                   = <!-- Variants in the same family and generation -->
<!------------------  History  ------------------->
| predecessor               = [[Zilog Z80]]
| successor                 = <!-- What CPU came after -->
<!------------------  Support status  ------------------->
| support status            = <!-- Current support status -->
}}

The '''Zilog eZ80''' is an [[8-bit computing|8-bit]] microprocessor designed by [[Zilog]] as an updated version of the company's first product, the highly-successful [[Zilog Z80]]. The eZ80 is [[binary compatible]] with the Z80, but it operates almost three times faster at the same [[clock frequency]].

== Design ==
{| class="infobox" style="font-size:88%;"
|-
|+ Zilog eZ80 registers in ADL mode
|-
|
{| style="font-size:88%;"
|-
| style="width:10px; text-align:center;"| <sup>2</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>2</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>2</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>2</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:auto;" | ''(bit&nbsp;position)''
|-
|colspan="17" | '''Main registers'''
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="8"| 0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="8"| Accumulator&nbsp;(A)
| style="text-align:center;background:#DDD" colspan="8"| Flags&nbsp;(F)
| style="background:white; color:black;"| '''AF'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| BCU
| style="text-align:center;" colspan="8"| B
| style="text-align:center;" colspan="8"| C
| style="background:white; color:black;"| '''BC'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| DEU
| style="text-align:center;" colspan="8"| D
| style="text-align:center;" colspan="8"| E
| style="background:white; color:black;"| '''DE'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| HLU
| style="text-align:center;" colspan="8"| H
| style="text-align:center;" colspan="8"| L
| style="background:white; color:black;"| '''HL'''
|-
|colspan="17" | '''Alternate (shadow) registers'''
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="8"| 0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="8"| Accumulator'&nbsp;(A')
| style="text-align:center;background:#DDD" colspan="8"| Flags'&nbsp;(F')
| style="background:white; color:black;"| '''AF{{'}}'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| BCU'
| style="text-align:center;" colspan="8"| B'
| style="text-align:center;" colspan="8"| C'
| style="background:white; color:black;"| '''BC{{'}}'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| DEU'
| style="text-align:center;" colspan="8"| D'
| style="text-align:center;" colspan="8"| E'
| style="background:white; color:black;"| '''DE{{'}}'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| HLU'
| style="text-align:center;" colspan="8"| H'
| style="text-align:center;" colspan="8"| L'
| style="background:white; color:black;"| '''HL{{'}}'''
|-
|colspan="17" | '''Index registers'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| IXU
| style="text-align:center;" colspan="8"| IXH
| style="text-align:center;" colspan="8"| IXL
| style="background:white; color:black;"| '''IX'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| IYU
| style="text-align:center;" colspan="8"| IYH
| style="text-align:center;" colspan="8"| IYL
| style="background:white; color:black;"| '''IY'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="24"| Stack Pointer
| style="background:white; color:black;"| '''SPL'''
|-
|colspan="17" | '''Other registers'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| Interrupt vector (base)
| style="text-align:center;background:#DDD" colspan="8"| 0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0
| style="background:white; color:black;"| '''I'''
|- style="background:silver;color:black"
| style="background:white; color:black;" colspan="16"| &nbsp;
| style="text-align:center;" colspan="8"| Memory base
| style="background:white; color:black;"| '''MBASE'''
|- style="background:silver;color:black"
| style="background:white; color:black;" colspan="16"| &nbsp;
| style="text-align:center;" colspan="1"|
| style="text-align:center;" colspan="7"| Refresh counter
| style="background:white; color:black;"| '''R'''
|-
|colspan="17" | '''Program counter'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="24"| Program Counter
| style="background:white; color:black;"| '''PC'''
|-
|colspan="17" | '''Status flags'''
|- style="background:silver;color:black"
| style="background:white; color:black;" colspan="16"| &nbsp;
| style="text-align:center;"| [[Sign flag|S]]
| style="text-align:center;"| [[Zero flag|Z]]
| style="text-align:center;"| -
| style="text-align:center;"| [[Adjust flag|H]]
| style="text-align:center;"| -
| style="text-align:center;"| <sup>[[Parity flag|P]]</sup>/<sub>[[Overflow flag|V]]</sub>
| style="text-align:center;"| N
| style="text-align:center;"| [[Carry flag|C]]
| style="background:white; color:black" | '''F'''lags
|-
|- style="background:silver;color:black"
| style="background:white; color:black;" colspan="12"| &nbsp;
| style="text-align:center;" colspan="3"| ADL
| style="text-align:center;" colspan="3"| EF1
| style="text-align:center;" colspan="3"| EF2
| style="text-align:center;" colspan="3"| MADL
| style="background:white; color:black" | Bit flags
|}
|}
The eZ80 has a three-stage pipeline: fetch, decode, and execute. When an instruction changes the [[program counter]], it flushes the instructions that the CPU is currently processing. Available at up to 50&nbsp;MHz (2004), the performance is comparable to a Z80 clocked at 150&nbsp;MHz if fast memory is used (i.e. no wait states for [[opcode]] fetches, for data, or for I/O) or even higher in some applications (a 16-bit addition is 11 times as fast as in the original). The original Z80-compatible 16-bit register configuration is supported. The eZ80 also supports direct continuous addressing of 16&nbsp;[[Megabyte|MB]] of memory without a [[memory management unit]], by extending most registers (HL, BC, DE, IX, IY, SP, and PC) from 16 to 24 bits. In order to do so, the CPU has a full 24-bit address mode called ADL mode. In ADL mode, all Z80 16-bit registers are extended to 24 bits with additional upper 8-bit registers. For example, the HL register pair is extended with an uppermost register called HLU. The resulting 24-bit multi-byte register is collectively accessed by its old name, HL. The upper registers cannot be accessed individually.<ref>{{cite book |title=eZ80 CPU User Manual |date=July 15, 2009 |publisher=Zilog |edition=15, April 2015 |url=http://www.zilog.com/docs/um0077.pdf |access-date=16 June 2024}}</ref>

The processor has a 24-bit ALU [[arithmetic logic unit]] and overlapped processing of several instructions (the three-stage pipeline) which are the two primary reasons for its speed. Unlike the older [[Z280]] and [[Z380]] it does not have (or need) a cache memory. Instead, it is intended to work with fast [[Static random-access memory|SRAM]] directly as main memory (as this had become much cheaper). Nor does it have the multiplexed bus of the Z280, making it as easy to work with (interface to) as the original Z80 and Z180, and equally predictable when it comes to exact execution times.

The chip has a [[Memory refresh#CPU-based refresh|memory interface]] that is similar to the original Z80, including the bus request/acknowledge pins, and adds four integrated chip selects. Versions are available with on-chip flash memory and on-chip zero wait-state SRAM (up to 256&nbsp;[[Kilobyte|KB]] flash memory and 16&nbsp;KB SRAM) but there are also external buses on all models.

== Variants ==

The eZ80 family includes several variants offering different levels of integration. These single-chip computers retain an external address and data bus so they can function as general-purpose microprocessors despite their focus on specific applications.

The ''eZ80Acclaim!'' line integrates up to 128 KB of flash memory and 8 KB of SRAM, operating at speeds up to 20 MHz.<ref>{{cite web|url=http://www.zilog.com/docs/ez80acclaim/ps0153.pdf|title=eZ80Acclaim! eZ80F92/eZ80F93 Flash MCU Product Specification|access-date=July 15, 2009|date=May 2008|publisher= [[Zilog]]|location=[[San Jose, California]]}}</ref><ref>{{cite web|url=http://www.zilog.com/docs/ez80acclaim/ps0192.pdf|title=eZ80Acclaim! eZ80F91 Flash MCU Product Specification|access-date=July 15, 2009|date=May 2008|publisher=[[Zilog]]| location=[[San Jose, California]]}}</ref>

The ''eZ80AcclaimPlus!'' adds an [[Ethernet]] controller and TCP/IP stack to the eZ80Acclaim! features, reaching speeds of up to 50 MHz.<ref>{{cite web|url=http://www.zilog.com/docs/ez80acclaimplus/PS0270.pdf|title=eZ80AcclaimPlus! eZ80F91 ASSP Product Specification|access-date=July 15, 2009|date=July 2007|publisher=[[Zilog]] |location=[[San Jose, California]]}}</ref>

== Use in commercial products ==

The [[TI-84 Plus CE]] graphing calculator utilizes the eZ80 in 24-bit address mode at 48&nbsp;MHz.<ref>{{Cite web |last=Connatser |first=Matthew |date=May 26, 2024 |title=Bored math students can now enjoy Sonic 2 on TI-84 Plus CE |url=https://www.theregister.com/2024/05/26/sonic_texas_instruments_calculator/ |access-date=2024-05-29 |website=The Register |language=en}}</ref> The eZ80L92 processor powers the [[ST Robotics]] robot controller, running at 50 MHz.<ref>{{Cite web |title=R12 Robot Manual |url=https://strobotics.com/manuals/R12%20manual.pdf |website=[[ST Robotics]] |page=8}}</ref>

== Notes ==
{{Notelist}}

== References ==
{{Reflist}}

{{Refbegin}}
* {{cite web|url=http://www.zilog.com/docs/software/rm0006.pdf|title=eZ80 CPU Zilog Real-Time Kernel Reference Manual|access-date=July 15, 2009|date=July 2007|publisher=[[Zilog]]| location=[[San Jose, California]]}}
* {{cite web|url=http://www.zilog.com/docs/software/um0075.pdf|title=eZ80 CPU Zilog Real-Time Kernel User Manual|access-date=July 15, 2009|date=July 2007|publisher=[[Zilog]]|location= [[San Jose, California]]}}
* {{cite web|url=http://www.zilog.com/docs/software/rm0040.pdf|title=eZ80 CPU Zilog TCP/IP Stack API Reference Manual|access-date=July 15, 2009|date=July 2007|publisher=[[Zilog]]| location=[[San Jose, California]]}}
{{Refend}}

== Further reading ==
* {{cite journal|last=Cantrell|first=Tom|date=February 2002|title=eZ Embedded Web|journal=Circuit Cellar|issue=139|url=http://www.circuitcellar.com/library/print/0202/cantrell139/|access-date=July 15, 2009}}
* {{cite web|url=http://mdfs.net/Docs/Comp/eZ80/OpList|title=Full eZ80 Opcode List|access-date= July 15, 2009|last=Harston|first=J.G.|date=April 15, 1998}}

{{Zilog}}
{{8bitMCUs}}

[[Category:Zilog microprocessors]]
[[Category:24-bit microprocessors]]
[[Category:8-bit microprocessors]]